Table of Contents
Introduction
The AXI MCDMA core is a soft Xilinx IP core for use with the Xilinx Vivado® Design Suite. The AXI MCDMA provides high-bandwidth direct memory access between memory and AXI4-Stream target peripherals. The AXI MCDMA core provides Scatter Gather interface with Multiple Channel support with independent configuration.
For more information, please refer to the AXI MCDMA product page which includes links to the official documentation and resource utilization.
Driver Sources
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
<If there are multiple drivers supporting this IP, we should make that statement here and add to the table>
| Driver Name | Path in Vitis | Path in Github |
|---|---|---|
| mcdma | <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/mcdma_<version> | https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/mcdma |
Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/mcdma |
The driver source code is organized into different folders. The table below shows the axi mcdma driver source organization.
| Directory | Description |
|---|---|
| doc | Provides the API and data structure details |
| data | Driver .tcl and .mdd file |
| examples | Example applications that show how to use the driver features |
| src | Driver source files |
Driver Implementation
For a full list of features supported by this IP, please refer to the AXI MCDMA product page.
Features
The AXI MCDMA Standalone driver supports the following features: - Supports upto 16 Channels
- Supports Scatter/Gather Direct Memory Access (DMA)
- Supports 64-bit Addressing
- Supports Optional Data Re-Alignment Feature
- Supports per channel interrupt
- Supports AXIS Control and Status Streams.
Known Issues and Limitations
- All IP features are supported
Example Design Architecture
The examples assumes AXI MCDMA IP is configured in loopback mode.
Example Applications
Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.
Links to Examples
Examples Path: https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/mcdma/examples
| Test Name | Example Source | Description |
|---|---|---|
| Packet transfer with Interrupts | xmcdma_interrupt_example.c | This example demonstrates how to use axi mcdma driver on axi mcdma core to transfer packets in interrupt mode. |
| Packet transfer with Polling | xmcdma_polled_example.c | This example demonstrates how to use axi mcdma driver on axi mcdma core to transfer packets in polled mode |
Example Application Usage
Packet transfer with Interrupts
This example demonstrates how to use axi mcdma driver on axi mcdma core to transfer packets in interrupt mode.
Expected Output
--- Entering main() --- AXI MCDMA SG Interrupt Test passed --- Exiting main() --- |
Packet transfer with Polling
This example demonstrates how to use axi mcdma driver on axi mcdma core to transfer packets in polled mode
Expected Output
--- Entering main() --- AXI MCDMA SG Polling Test passed --- Exiting main() --- |
Change Log
2021.1
None
2020.2
https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.2/doc/ChangeLog#L370
Related Links