This page gives an overview of clk_wiz driver which is available as part of the Xilinx Vivado and SDK distribution.
For more information, please refer TRM which includes links to the official documentation and resource utilization.
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
Driver Name | Path in Vitis | Path in Github |
---|---|---|
clk_wiz | <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/clk_wiz | https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/clk_wiz |
Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/clk_wiz |
The driver source code is organized into different folders. The table below shows the clk_wiz driver source organization.
Directory | Description |
---|---|
doc | Provides the API and data structure details |
data | Driver .tcl and .mdd file |
examples | Example applications that show how to use the driver features |
src | Driver source files |
For a full list of features supported by this IP, please refer TRM
Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.
Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/clk_wiz/examples
Test Name | Example Source | Description |
---|---|---|
Clocking wizard versal example | Example to set the output frequency to a specific rate for versal platform. | |
Clocking wizard Interrupt mode example | This example tests the clock monitoring example |
This examples does basic rate setting of clocking wizard.
Expected Output
------------------------------------------ CLK_WIZARD example ------------------------------------------ Successfully ran CLK_WIZARD example |
This example tests the clock monitoring example
Expected Output
------------------------------------------ CLK_WIZARD example ------------------------------------------ Successfully ran CLK_WIZ Monitor interrupt example |
NA
NA
None
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L1170
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L2100