Driver source code is organized into different folders. Below diagram shows the bram driver source organization
bram | -- Doc - Provides the API and data structure details | - Examples - Reference application to show how to use the driver APIs and calling sequence | - Source - Driver source files
Features Supported
Controller/Driver features supported
The Xilinx BRAM controller is a soft IP core designed for Xilinx FPGAs and contains the following general features,
LMB v2.0 bus interfaces with byte enable support
Separate read and write channel interfaces to utilize dual port FPGA BRAM technology
Supports memory sizes up to a maximum of 2 MBytes
Compatible with Xilinx AXI Interconnect
Used in conjunction with bram_block peripheral to provide fast BRAM memory solution for MicroBlaze ILMB and DLMB ports
Supports byte, half-word, and word transfers
Supports optional BRAM error correction and detection