This page gives an overview of axi traffic generator driver which is available as part of the Xilinx Vivado and SDK distribution.
The Xilinx® LogiCORE™ IP AXI traffic generator core is a soft Xilinx IP core for
Use with the Xilinx Vivado® Design Suite.
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
Driver Name | Path in Vitis | Path in Github |
---|---|---|
trafgen | <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/trafgen | https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/trafgen |
Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/ospipsv |
The driver source code is organized into different folders. The table below shows the ospipsv driver source organization.
Directory | Description |
---|---|
doc | Provides the API and data structure details |
data | Driver .tcl and .mdd file |
examples | Example applications that show how to use the driver features |
src | Driver source files |
For a full list of features supported by this IP, please refer TRM
Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.
Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/trafgen/examples
Test Name | Example Source | Description |
---|---|---|
Trafgen Polled mode example | This example programs known data to master RAM and command to command ram and param ram. The data will be taken from master RAM and programmed to the slave. | |
Trafgen Interrupt mode example | This example programs known data to master RAM and command to command ram and param ram. The data will be taken from master RAM and programmed to the slave in interrupt mode. | |
Trafgen Streaming example | xtrafgen_master_streaming_example.c | This examples does basic read and write test from the flash device in Non-blocking Polled mode. |
This example programs known data to master RAM and command to command ram and param ram. The data will
be taken from master RAM and programmed to the slave.
Expected Output
Entering main --- Exiting main() --- Successfully ran Traffic Generator Polling Example |
Expected Output
Successfully ran Traffic Generator Interrupt Example |
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https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L2214
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