Introduction
The Xilfpga library provides an interface to the Linux or bare-metal users for configuring the programmable logic (PL) over PCAP from PS. The library is designed for
Zynq® UltraScale+ MPSoC to run on top of Xilinx standalone BSPs. In the most common use case, we expect users to run this library on PMU MicroBlaze
with PMUFW to serve requests from Linux for bitstream programming.
How to enable
xilfpga library can be found at
https://github.com/Xilinx/embeddedsw/tree/master/lib/sw_services/xilfpga
xilfpga
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- data - Provides the API and data structure details
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- src - Driver source files which are further organised into
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- examples - Contains example applications demonstrating the use of xilfpga library
HW IP Features
- Full Bitstream and Partial Bitstream loading
- Encrypted and Authenticated Full/Partial Bitstream loading
- Readback of Configuration Registers
- Readback of Bitstream(Configuration Data)
- Compressed Bitstream
Features supported in the driver
The following features are supported in Zynq UltraScale+ MPSoC platform:
- Full bitstream loading
- Partial bitstream loading
- Encrypted bitstream loading
- Authenticated bitstream loading
- Authenticated and encrypted bitstream loading
- Readback of configuration registers
- Readback of configuration data
The following features are supported in Versal platform:
- Full/Partial bitstream loading
- Device Key Encrypted bitstream loading
- Authenticated bitstream loading
- Authenticated and Device-key encrypted bitstream loading
Known Issues and Limitations
Test Cases
There are examples which will illustrate the xilfpga usage. They can be found at
ChangeLog
- 2016.3
- Added new xilfpga library.
- 2016.4
- Added PL power-up and Isolation sequence to the xilfpga library.
- Added PS-PL Reset sequence.
- Added Preprocessor check for XPAR_NUM_FABRIC_RESETS to avoid the compilation errors.
- Added gpio assert logic to properly reset the PL from PS.
- 2017.1
- Adds Encrypted BitStream Loading support to the xilfpga library
- Updated makefile
- Modified IV endianess
- Adds Authenticated BitStream Loading support to the xilfpga library
- Send Key and IV in big endian form
- Fixed compilation warnings.
- Configure the secure switch with the appropriate value.
- Adds Reconfiguration BitStream Loading support to the xilfpga library
- 2017.2
- Xilfpga: Fix the check logic issue in xilfpga library
- 2017.3
- Updated the source files to updated addtogroup version numbers
- Xilfpga: Remove Authenticated BitStream Loading support from xilfpga library.
- 2017.4
- 2018.1
- Xilfpga: Adds Secure Bitstream Loading support to the xilfpga library
- xilfpga: Updated the example to sync with xilfpga library latest version
- Xilfpga: Adopted Crypto access rules to the xilfpga library
- xilfpga: Adds legacy Bit file support to the xilfpga library
- 2018.2
- Xilfpga: Fix Documentation style issues
- Xilfpga: Adds support to Re-validated the user Crypto flags with Image crypto operations
- Xilfpga: Adds Partial Bitstream loading support to the xilfpga library
- 2018.3
- xilfpga: Update the Doxygen comments for the recent changes
- xilfpga: Fix issues with Aes user-key cleaning logic
- xilfpga: Fix misra-c required standard violations
- lib: xilfpga: Improve bitstream size handling in the library
- lib: xilfpga: Fix issues with secure partial bitstream loading
- lib: xilfpga: Return proper status in case of secure bitstream passed with nonsecure flags
- lib: xilfpga: Add support for unaligned bitstream
- xilfpga: Fix cpp check warnings
- xilfpga: Fix standalone coding style issues.
- Xilfpga: Modified the PL data handling Logic to support different PL programming interfaces
- xilfpga: Fix typo errors in the library.
- lib: xilfpga: Use XCsuDma_WaitForDoneTimeout() API instead of XCsuDma_WaitForDone()
- xilfpga: Add example for loading partial bitstream
- xilfpga: Fix xilsecure dependencies
- xilfpga: Change the function name as per the standalone drivers standards
- xilfpga: Adds support to load vivado generated .bit and .bin files
- xilfpga: Fix issues with readback
- xilfpga: Add example for readback of configuration data
- xilfpga: zynqmp: Add support for readback of configuration data
- xilfpga: Enhance the ConfigReg readback changes
- Xilfpga: Adding Device Key support with user configuration.
- Xilfpga : Adds Debug prints and New Error codes handling mechanism to the library
- xilfpga: Move flags related macro's from xilfpga_pcap.c to xilfpga.h
- xilfpga: Updated the examples to the new API's
- Xilfpga: Refactoring the xilfpga library to support different PL programming interfaces.
- Xilfpga: Adds Partial Bistream loading support to the xilfpga library
- Xilfpga: Adds support to Re-validated the user Crypto flags with Image crypto operations
- 2019.1
- Generated Doxygen documentation and PDF's for sw_services
- xilfpga: Fixed IAR compiler warnings in read back examples
- xilfpga:src:MISRA-C:No brackets to loop body.
- sw_services :xilfpga: Add error recovery mechanism to xilfpga
- xilfpga: update the data handling logic.
- lib: xilfpga: Update the examples for the latest xilfpga version
- Xilfpga: Updated Makefile to support IAR
- lib: xilfpga: Adds missing extern protection macros
- 2019.2
- Published xilfpga PDF document
- Xilfpga: Improve error handling in the bitstream validation path.
- Xilfpga: Fix issues with Initialize empty status
- xilfpga: Fix for Secure Header Zeroize issue
- Xilfpga: Adds support to clear out the SHA3 engine.
- xilfpga: Update documentation for readback API's
- 2020.1
- xilfpga: Update SECURE_MODE handling logic.
- Xilfpga: Remove unwanted header file inclusion
- xillfpga: zynqmp: Adopt Bitstream Configuration and readback support using IPI mechanism
- xilfpga: Replace event poll logic with Xil_WaitForEvent() API.
- xilfpga: Add support for secure readback feature
- Xilfpga: Fix for security violation in the readback path
- Xilfpga: Remove unused variables
- Xilfpga: Remove unwanted status check
- Xilfpga: Fix for function naming issues
- xilfpga: update documentation
- Xilfpga: Clear Aes-key from internal memory.
- xilfpga: Fix the issues with Aes-key