This page describes the open source Xen hypervisor and how it is used on AMD-Xilinx Zynq UltraScale+ and Versal devices.
Xen is a free and open source type-1 hypervisor. The Xen hypervisor is developed as a Linux Foundation project as part of the Xen Project.
On AMD-Xilinx devices, Xen runs as part of Arm execution-level 2 (EL2). Xen hypervisor consists of three components:
Xen is a type-1 Hypervisor defined, maintained and provided to the open source community by the Xen Project. Xilinx actively contributes code to the Xen Project to provide Zynq UltraScale+ MPSoC platform support as well as key enhancements which benefit Xilinx customer use-cases.
Xen allows multiple instances of operating system(s) or bare-metal applications to execute on Zynq UltraScale+ MPSoC. Additional information on the Xen hypervisor can be found at the Xen Project Getting Started page.
Xilinx provides within the PetaLinux Tools and also in our Git tree, core elements and example designs to enable usage of Linux + bare-metal system configurations across the processing cores of Zynq UltraScale+ MPSoC. Key components of these example designs are described below in order to assist our customers to configure, build and deploy these basic configurations and to also identify current functionality gaps which may need to be further addressed within the customer's final system architecture.
One Linux DomU + two Bare-Metal Applications |
Linux Dom0 with custom apps + three Bare-Metal Applications |
Two Linux DomU + one Bare-Metal Application |
Three Linux DomU
Feature | Description | First Xen release |
Dom0less | Dom0less functionality allows Xen to immediately start up one or more DomU's based on a devicetree-based system topology description. This feature allows Xen-based systems to boot more rapidly and predictably than Dom0-based systems. | 2019.1 |
Cache Coloring | Cache Coloring functionality maps hardware cache lines to specific Xen DomU's to prevent cache and memory thrashing. This feature allows Xen-based systems, particularly those sensitive to interrupt latency and bare-metal performance, to operate more efficiently. | 2020.1 |