The purpose of this page is to describe the Linux V4L2 driver for Xilinx MIPI Camera Serial Interface 2 Receiver subsystem (MIPI CSI2 Rx SS) soft IP. The Linux MIPI CSI2 Rx Subsystem driver (xilinx-csi2rxss.c) is based on the V4L2 framework, and creates a subdev node(/dev/v4l-subdev*) which can be used to configure the MIPI CSI2 Rx Subsystem IP core. The general description of V4L2 framework is documented here. This subdev driver has 2 ports. One sink port which is connected to the image sensor's source port and one source port. The media format applied on the sink port is passed on to the source port. The media format applied is validated based on the IP configuration like RAW8, RAW10, etc. The driver also exposes a V4L2 control to set the number of active lanes, if the feature is enabled in the IP configuration. It also exposes V4L2 control to read number of frames transferred and to reset the event counters.
The MIPI CSI-2 RX subsystem allows you to quickly create systems based on the MIPI protocol. It interfaces between MIPI-based image sensors and an image sensor pipe. An internal high speed physical layer design, D-PHY, is provided that allows direct connection to image sources.
IP Features | 2018.1 | 2018.2 | 2018.3 | 2019.1 | 2019.2 | 2020.1 | 2020.2 | 2021.1 | 2021.2 |
---|---|---|---|---|---|---|---|---|---|
IP version | 3.0 | 3.0 | 4.0 | 4.0 | 4.1 | 5.0 | 5.1 | ||
Support for 1 to 4 D-PHY lanes | NA | ||||||||
Line rates ranging from 80 to 1500 Mb/s | NA | ||||||||
Multiple Data Type support (RAW, RGB, YUV) | IP allows RAW6/7/8/10/12/14, all RGB and YUV 422 8bpc Driver allows to set any format except when RAW10 and RAW12. | IP allows RAW6/7/8/10/12/14/16/20, all RGB and YUV 422 8/10 bpc Driver allows to set any format except when RAW10, RAW12 and RAW16 | Added YUV 420 8 bpc support | ||||||
AXI IIC support for Camera Control Interface (CCI) | NA | Removed | |||||||
Filtering based on Virtual Channel Identifier | NA | ||||||||
Support for 1, 2, or 4 pixels per sample at the output | Yes** | ||||||||
AXI4-Lite interface for register access to configure different subsystem options | Yes | ||||||||
Dynamic selection of active lanes within the configured lanes during subsystem generation | Yes | ||||||||
Interrupt generation to indicate subsystem status information | Yes | ||||||||
Internal D-PHY allows direct connection to image sources | Yes | ||||||||
Resource optimization (removed register interface) | NA | No |
*Only RAW8/10/12/16 media bus formats are tested.
**Tested for 1 and 2 pixels per sample
Since 2021.1, the upstream driver is being used. This driver doesn't have any of the v4l2 controls as earlier.
Now pad 0 is sink pad and pad 1 is source pad. It uses the gpio connected to video-aresetn pin to reset.
In case of buffer overflow, the core is disabled.
It enumerates the bus formats. Only the sink pad format can be set. When trying to set source format, driver will return the format set on sink pad.
The driver just reads and prints the short packet data now to debug log when the Short packet FIFO is not empty.
It still keeps a counter of all types of events and prints them on log status.
Now on stream on, the driver not only enables itself but calls the stream on function of the driver for source element (reliance on Xilinx video pipeline is reduced).
On stopping stream, the core is disabled and a hard reset via gpio connected to video-aresetn pin is given to core.
Other features supported in driver are -
A video pipeline with MIPI CSI2 Rx connected to Demosaic, Gamma LUT, VPSS CSC, VPSS Scaler and Framebuffer Write IP is created for ZCU102 board.
An IMX74 sensor FMC card is used to capture image and send CSI stream to MIPI CSI 2 Rx Subsystem.
media-ctl is used to set the color format on the pads.
#Assuming the media device /dev/media1 has MIPI CSI2 Rx Subsystem entity name whose name is "a00f0000.csiss" #To set RGGB RAW8 bayer data of size 1920x1080 on source pad media-ctl -v -V '"a00f0000.csiss":0 [fmt:SRGGB8_1X8/1920x1080 field:none colorspace:srgb]' -d /dev/media1 |
Using v4l2-ctl to set the number of active lanes
#Assume MIPI CSI2 Rx subsystem which is registered as /dev/v4l-subdev1 #To set the number of active lanes as 4 v4l2-ctl -c mipi_csi2_rx_subsystem_active=4 -d /dev/v4l-subdev1 |
Using yavta to set the number of active lanes
#Assume MIPI CSI2 Rx subsystem which is registered as /dev/v4l-subdev1 #To set the number of active lanes as 4 (NA after 2020.2) yavta -w '0x0098c981 4' /dev/v4l-subdev1 #To see all the controls yavta -l /dev/v4l-subdev1 #Need to setup the media pipeline and start capture of video stream media-ctl -v -V '"IMX274":0 [fmt:SRGGB8/1920x1080@1/60 field:none colorspace:srgb]' -d /dev/media1 media-ctl -v -V '"a00f0000.csiss":0 [fmt:SRGGB8_1X8/1920x1080 field:none colorspace:srgb]' -d /dev/media1 media-ctl -v -V '"a0250000.v_demosaic":1 [fmt:RBG888_1X24/1920x1080 field:none colorspace:srgb]' -d /dev/media1 media-ctl -v -V '"a0270000.v_gamma":1 [fmt:RBG888_1X24/1920x1080 field:none colorspace:srgb]' -d /dev/media1 media-ctl -v -V '"a0240000.csc":1 [fmt:RBG888_1X24/1920x1080 field:none colorspace:srgb]' -d /dev/media1 media-ctl -v -V '"a0200000.scaler":0 [fmt:RBG888_1X24/1920x1080 field:none colorspace:srgb]' -d /dev/media1 media-ctl -v -V '"a0200000.scaler":1 [fmt:UYVY/1920x1080 field:none colorspace:srgb]' -d /dev/media1 #Now start streaming yavta -n 3 -c10 -f UYVY -s 1920x1080 --skip 7 -F /dev/video4 |
A custom application was implemented to test getting the short packets and other events using poll() on file descriptor returned on open() of the v4l subdev.
This was done as poll() mechanism on sub device wasn't present in any standard application.