The AXI MCDMA core is a soft Xilinx IP core for use with the Xilinx Vivado® Design Suite. The AXI MCDMA provides high-bandwidth direct memory access between memory and AXI4-Stream target peripherals. The AXI MCDMA core provides Scatter Gather interface with Multiple Channel support with independent configuration.
For more information, please refer to the AXI MCDMA product page which includes links to the official documentation and resource utilization.
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
Driver Name | Path in Vitis | Path in Github |
---|---|---|
mcdma | <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/mcdma_<version> | https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/mcdma |
Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/mcdma |
The driver source code is organized into different folders. The table below shows the axi mcdma driver source organization.
Directory | Description |
---|---|
doc | Provides the API and data structure details |
data | Driver .tcl, .mdd file and .yaml files |
examples | Example applications that show how to use the driver features |
src | Driver source files, make and cmake files |
Note: AMD Xilinx embeddedsw build flow is changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki page Porting embeddedsw components to system device tree (SDT) based flow - Xilinx Wiki - Confluence (atlassian.net).
The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in the future.
For a full list of features supported by this IP, please refer to the AXI MCDMA product page.
The examples assumes AXI MCDMA IP is configured in loopback mode.
Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.
Links to Examples
Examples Path: https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/mcdma/examples
Test Name | Example Source | Description |
---|---|---|
Packet transfer with Interrupts | xmcdma_interrupt_example.c | This example demonstrates how to use axi mcdma driver on axi mcdma core to transfer packets in interrupt mode. |
Packet transfer with Polling | xmcdma_polled_example.c | This example demonstrates how to use axi mcdma driver on axi mcdma core to transfer packets in polled mode |
This example demonstrates how to use axi mcdma driver on axi mcdma core to transfer packets in interrupt mode.
Expected Output
--- Entering main() --- AXI MCDMA SG Interrupt Test passed --- Exiting main() --- |
This example demonstrates how to use axi mcdma driver on axi mcdma core to transfer packets in polled mode
Expected Output
--- Entering main() --- AXI MCDMA SG Polling Test passed --- Exiting main() --- |
2023.2
https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2023.2/doc/ChangeLog#L560
2023.1
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2023.1/doc/ChangeLog#L101
2022.2
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2022.2/doc/ChangeLog#L111
2022.1
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2022.1/doc/ChangeLog#L52
2021.2
None
2021.1
None
2020.2
https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.2/doc/ChangeLog#L370
Related Links