The ZynqMP reset-controller has the ability to reset lines connected to different blocks and peripheral in the Soc.
This page gives an overview of the ZynqMP reset-controller driver which is available as part of the ZynqMP Linux distribution.
Paths, files, links and documentation on this page are given relative to the Linux kernel source tree.
Below links provide the information about the reset-controller linux framework
http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/reset/reset.txt
http://elixir.free-electrons.com/linux/latest/source/drivers/reset/core.c#L196
Device Drivers --->[*] Reset Controller Support--->[*] Xilinx ZYNQMP Reset Controller Support
rst: reset-controller {
compatible = "xlnx,zynqmp-reset";
#reset-cells = <1>;
};
|
The following commit will give you the better understanding and the exact use case of the reset controller.
https://github.com/Xilinx/linux-xlnx/commit/9b4eecd86677acf0d146fdab97dd5324e8f1b404
The Reset-controller driver itself will not initiate any IP reset request.
The Reset request always initiated by the consumer driver as shown in the above commit id
The below patch created only for testing purpose.
apply the patch 0001-Reset-Added-sysfs-entries-for-zynqmp-reset-controlle.patch
This patch has debug sysfs entry so that the reset controller driver can be tested from user space
1) echo reset_IP_num > /sys/class/reset-mgr/reset ----> It will reset the IP by providing the High to low signal.
2) echo reset_IP_num > /sys/class/reset-mgr/reset_assert ---> it will assert IP by providing the HIGH signal ( the relevant bit is set to High until it receives deassert signal).
3) echo reset_IP_num> /sys/class/reset-mgr/reset_deassert ---> it will deassert IP by providing the LOW signal
Reset_IP_num are available here:
https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/reset/zynqmp-reset.txt
$echo reset_IP_num > /sys/class/reset-mgr/reset ----> It will reset the IP by providing the High to low signal. $echo reset_IP_num > /sys/class/reset-mgr/reset_assert ---> it will assert IP by providing the HIGH signal ( the relevant bit is set to High until it receives deassert signal). $echo reset_IP_num > /sys/class/reset-mgr/reset_deassert ---> it will deassert IP by providing the LOW signal |
The current driver available in the Xilinx Linux git is in sync with the open-source 6.1 kernel driver except for the following:
2016.3
Summary:
reset: reset-zynqmp: Adding support for Xilinx zynqmp reset controller.
Commits:
930e883 reset: reset-zynqmp: Adding support for Xilinx zynqmp reset controller
2016.4
None
2017.1
None
2017.2
None
2017.3
Summary:
zynqmp: Use new firmware.h instead of pm.h
Commits:
5e81ba5zynqmp: Use new firmware.h instead of pm.h
2017.4
None
2018.1
Summary:
soc: zynqmp: Define EEMI ops structure
soc: zynqmp: Use new firmware APIs
Commits:
2018.2
None
2018.3
None
2019.1
Sync Mainline changes
2019.2
2020.1
None
2020.2
Summary:
Fix coverity warnings
Commits:
2021.1
Summary:
Added support for Versal platform.
Commits:
2021.2
Summary:
Fixed the argument data type.
Commits:
2022.1
2022.2
Summary:
Add support for Versal NET platform.
Commits:
2023.1
Summary:
Kernel version Upgrade to V6.1.
Commits:
2023.2
None
https://github.com/Xilinx/linux-xlnx/blob/master/drivers/reset/reset-zynqmp.c