This technical article provides you an overview of the ZCU106 HDMI Example design which also leverages the Video Codec Unit (VCU) hard block on the Zynq UltraScale+ MPSoC EV Devices. This article uses Vivado IP Integrator (IPI) flow for building the hardware design and Xilinx Yocto PetaLinux flow for software design.


Table of Contents

Document History

DateVersionAuthorDescription of Revisions
June 22, 20181.0E.Srikanth/M DamoderFirst HDMI Example Design of ZCU106




Introduction


The ZCU106 HDMI Example design has a HDMI Receiver capture pipeline implemented in the PL to which a video source attached. It also has a HDMI Tx display pipeline implemented in the PL to which a HDMI Display is connected.
Finally, the user guide also demonstrates encode and decode capabilities of the VCU block using the video captured and displayed by the HDMI Receive and Transmitter pipelines.

ZCU106 Evaluation Platform

The ZCU106 HDMI Example Design uses the following IPs along with the Zynq UltraScale+ Processing System for demonstrating video capture, encode, decode, display and streaming using the VCU block on Zynq UltraScale+ MPSoC EV devices.
  1. Zynq UltraScale+ MPSoC Processing System
  2. HDMI Receiver Pipeline containing the following IPs
    • HDMI RX Subsystem
    • Video Scaler
    • Frame Buffer Write IP
  3. HDMI Transmitter Pipeline containing the following IPs
    • HDMI TX Subsystem
    • Video Mixer
    • Frame Buffer Read IP
  4. I2C Controller
  5. Video Codec Unit (VCU)


ZCU106 HDMI Example Design Block Diagram


Download, Installation and Licensing

The Vivado Design Suite User Guide explains how to download and install the Vivado® Design Suite tools, which includes the Vivado Integrated Design Environment (IDE), High Level Synthesis tool, and System Generator for DSP. This guide also provides the information about licensing and administering evaluation and full copies of Xilinx design tools and intellectual property (IP) products. The Vivado Design Suite can be downloaded from here.
The following IP cores require a license to build the design

To obtain the LogiCORE IP license, please visit the respective IP product page and get the license.

Building the Hardware and Software

This user guide is accompanied by a ZCU106 HDMI Example Design files (zcu106_hdmi_ex_2018.1.zip).
Download this zip file to your local directory or folder of your Windows or Linux machine to run the hardware and software building steps as mentioned in the further sections of this document.

Refer to the Vivado Design Suite User Guide UG973 (v2018.1) for setting up Vivado 2018.1 environment.

NOTE:

Building Hardware Design

This sections explains the steps to build the ZCU106 HDMI Example design.























Building software components

This tutorial shows how to build the Linux image and boot image using the PetaLinux build tool.
Refer to the PetaLinux Tools Documentation (UG1144) for installation.


Preparing the SD Cards:




This document demonstrates following two use cases.
Use Case 1: HDMI capture pipeline with VCU Encode and streaming




Overview:
This use case demonstrates video streaming using two ZCU106 boards as show in above use case diagram.
The live/raw video is captured ( in YUV format ) using HDMI Rx subsystem on the ZCU106 Board1. The captured data is encoded ( in H .265 format) using the VCU Block. The encoded data is packetized into RTP packets using RTP stack and these RTP packets are transmitted out to other ZCU106 Board 2.

The RTP packets are received, de-packetized and generates compressed stream using RTP stack on ZCU106 Board 2 .The compressed data is decoded using VCU block and rendered on to the display monitor ( which is connected to ZCU106 Board 2) using HDMI-TX subsystem.

Use Case 2: HDMI capture pipeline with VCU Encode and streaming in bidirectional mode



Overview:
This use case demonstrates video streaming using two ZCU106 boards.
The live/raw video is captured ( in YUV format ) using HDMI Rx subsystem on the ZCU106 Board1. The captured data is encoded ( in H .265 format) using the VCU Block. The encoded data is packetized into RTP packets using RTP stack and these RTP packets are transmitted out to Board 2. The RTP packets are received ,de-packetized and generates compressed stream using RTP stack on ZCU106 Board 2 .The compressed data is decoded using VCU block and rendered on to the display monitor ( which is connected to ZCU106 Board 2) using HDMI-TX subsystem. This same process happens from the Board 2 to Board 1 simultaneously in bi-directional mode .
Additional material that is not hosted in this tutorial:

• Zynq UltraScale+ MPSoC VCU TRD user guide, UG1250: The UG provides the list of features, software architecture and hardware architecture.

Running the Use Cases:

This section instructs how to run the above two use cases with prebuilt binaries supplied along with this document in case user don’t want to go through all the build steps.


Compatibility
The Example design has been tested successfully with the following user-supplied components.

Make/ModelResolutions
LG 27UD883840x2160 (30Hz)
Philips BDM4350UC3840 x 2160 (60Hz)


Setting up the ZCU106 Boards:






Below figure show the complete board setup:





Executing Use case 1:









Executing Use case 2:


Appendix A: Determine which COM to use to access the USB serial port on the ZCU106 board.


Appendix B: File Description in Design directory
zcu106_hdmi_ex_2018.1.zip is extracted as