Table of Contents

Introduction

This page gives overview of Zynq DisplayPort Subsystem which available as part of the Xilinx Vivado and SDK distribution.

The Subsystem is divided into 3 drivers
  1. dppsu - DisplayPort Controller 
  2. avbuf - Video Pipeline interface to PL and Memory
  3. dpdma - DispayPort DMA for reading audio video from the memory


How to enable

1. dppsu - https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/dppsu
2. avbuf - https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/avbuf
3. dpdma - https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/dpdma

Driver source code is organized into different folders. Below diagram shows the driver source organization

avbuf/dppsu/dpdma
|
-- Doc - Provides the API and data structure details
|
- Examples - Reference application to show how to use the driver APIs and calling sequence
|
- Source - Driver source files


Supported Features


The following features are supported:


Known issues and limitations

The driver supports all the features except
1. Chroma Keying
2. Dithering

Test Procedure


Use case - Memory based data path (non-live)
The example in the DPDMA driver demonstrates the usage of the non-live(memory) data path. To enable this driver, dppsu should be selected under psu_dp and dpdma should be selected under psu_dpdma in the system.mss file.

Use case - PL to DP data path
To test this use case, psu_dp needs to be selected to dppsu and in the avbuf api will enable the access to the PL. Refer DPDMA example for the usage of the API.

Use case - PL to PL data path
To test this use case, psu_dp needs to be selected to avbuf.

Use case - Memory to PL data path
To test this use case, psu_dp needs to be selected to avbuf and the

Change Log

2018.1