Table of Contents
The generic interrupt controller (GIC) is a centralized resource for managing interrupts sent to theCPUs from the PS and PL. The controller enables, disables, masks, and prioritizes the interrupt sources and sends them to the selected CPU (or CPUs) in a programmed manner as the CPU interface accepts the next interrupt. In addition, the controller supports security extension for implementing a security-aware system. The controller is based on the ARM Generic Interrupt Controller Architecture version 1.0 (GIC v1), non-vectored. The registers are accessed via the CPU private bus for fast read/write response by avoiding temporary blockage or other bottlenecks in interconnect. The interrupt distributor centralizes all interrupt sources before dispatching the one with the highest priority to the individual CPUs. The GIC ensures that an interrupt targeted to several CPUs can only be taken by one CPU at a time. All interrupt sources are identified by a unique interrupt ID number.
All interrupt sources have their own configurable priority and list of targeted CPUs.
This is an interrupt asserted by a signal to the GIC. It can be classified in two ways.
1. Private Peripheral Interrupt <or> Shared Peripheral Interrupt
Private Peripheral Interrupt (PPI)- This is a peripheral interrupt that is specific to a single processor.
Shared Peripheral Interrupt (SPI) - This is a peripheral interrupt that the Distributor can route to any of a specified combination of processors.
NOTE: For Zynq UltraScale+ MPSoC Interrupts the GIC - 32 (i.e. PL_PS_Group0 121-32 = 89)
2. Edge-triggered or Level-sensitive
Edge-triggered - This is an interrupt that is asserted on detection of a rising edge of an interrupt signal and then, regardless of the state of the signal, remains asserted until it is cleared by the conditions defined by this specification.
Level-sensitive - This is an interrupt that is asserted whenever the interrupt signal level is active, and deasserted whenever the level is not active.
This is an interrupt generated by software writing to a GICD_SGIR register in the GIC.
The system uses SGIs for interprocessor communication.
An SGI has edge-triggered properties.The software triggering of the interrupt is equivalent to the edge transition of the interrupt request signal.
Zynq-7000.dtsi snippet
irq_cntlr: interrupt-controller@f8f01000{
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0xf8f01000 0x1000>, <0xf8f00100 0x100>;
interrupts = <1 9 0xf04>; };
.. ..
axi_fifo_mm_s_0: axi_fifo_mm_s@8000c000
compatible = "xlnx,axi-fifo-mm-s-4.1";
interrupt-parent = <&irq_cntlr>;
interrupts = <0 96 4>;
reg = <0x0 0x8000c000 0x0 0x1000>;
xlnx,axi-str-rxd-protocol = "XIL_AXI_STREAM_ETH_DATA";
};
|
The PL IP AXI FIFO MM2S's interrupt-parent = <&irq_cntlr> which is ARM GIC. The IRQ numbers are in interrupts = <0 96 4>, the first number (zero) is a flag indicating if the interrupt is an SPI (shared peripheral interrupt) i.e. from PL to PS.The second number is related to the interrupt number.The third number is the type of interrupt. Three values are possible:
0 — Leave it as it was (power-up default or what the bootloader set it to, if it did)
1 — Rising edge
4 — Level sensitive, active high
http://lxr.free-electrons.com/source/Documentation/devicetree/bindings/arm/gic.txt?v=3.10
2023.2
2023.1
2022.2
2022.1