Table of Contents

Introduction

This page gives an overview of pl330/dmaps DMA driver which is available as part of the Xilinx Vivado and Vitis distribution.

For more information, please refer to PL330 DMA controller chapter in Zynq TRM (UG585).

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository. 

Driver Name

Path in Vitis

Path in Github

dmaps

<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/dmaps

https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/dmaps


Note: To view the sources for a particular release, use the rel-version tag in github.  For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx_v2021.1/XilinxProcessorIPLib/drivers/dmaps


The driver source code is organized into different folders.  The table below shows the dmaps driver source organization. 

Directory

Description

doc

Provides the API and data structure details

data

Driver .tcl and .mdd file

examples

Example applications that show how to use the driver features

src

Driver source files

Driver Implementation

For a full list of features supported by this IP, please refer to PL330 DMA controller chapter in Zynq TRM (UG585).

Features

Controller/Driver features supported

Known Issues and Limitations

Example Applications

DMAPS driver supports a basic interrupt examples describing how its different features can be exercised. These example applications can be imported into the Vitis IDE from the Board Support Package  settings tab. 

Links to Examples

Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/dmaps/examples

Test Name

Example Source

Description

DMAPS interrupt example

xdmaps_example_w_intr.c

Basic DMAPS interrupt example demonstrating one transfer over first channel.

Example Application Usage

DMAPS Interrupt example

Basic DMAPS interrupt example demonstrating one transfer over first channel.

Expected Output

Test round 0
Successfully ran XDMaPs_Example_W_Intr

Example Design Architecture

NA

Performance

NA

Change Log

2022.1

None

2021.2

None

2021.1

https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2021.1/doc/ChangeLog#L243

2020.2

https://github.com/Xilinx/embeddedsw/blob/release-2020.2/doc/ChangeLog#L612

2020.1

https://github.com/Xilinx/embeddedsw/blob/release-2020.1/doc/ChangeLog#L33

2019.2

https://github.com/Xilinx/embeddedsw/blob/release-2019.2/doc/ChangeLog#L12

2019.1

None

2018.3

None

2018.2

None

2018.1

None

Related Links