This page gives an overview of XADC driver which is available as part of the Xilinx Vivado and SDK distribution.
Table of Contents
Introduction
The Xilinx analog mixed signal module, referred to as the XADC, is a hard macro. It has JTAG and DRP interfaces for accessing the XADC’s status and control registers in the 7-series FPGAs.
Zynq-7000 AP SoC devices add a third interface, the PS-XADC interface for the PS software to control the XADC. The Zynq-7000 AP SoC devices combine a flexible analog-to-digital converter with programmable logic to address a broad range of analog data acquisition and monitoring requirements. The XADC is part of a larger analog mixed signal (AMS) topic that is a combination of analog and digital circuits.
Source path for the driver:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/xadc/src
Driver source code is organized into different folders. Below diagram shows the sysmonpsu driver source organization
Zynq-7000 AP SoC devices add a third interface, the PS-XADC interface for the PS software to control the XADC. The Zynq-7000 AP SoC devices combine a flexible analog-to-digital converter with programmable logic to address a broad range of analog data acquisition and monitoring requirements. The XADC is part of a larger analog mixed signal (AMS) topic that is a combination of analog and digital circuits.
Source path for the driver:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/xadc/src
Driver source code is organized into different folders. Below diagram shows the sysmonpsu driver source organization
xadc
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-- Doc - Provides the API and data structure details
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- Examples - Reference application to show how to use the driver APIs and calling sequence
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- Source - Driver source files
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-- Doc - Provides the API and data structure details
|
- Examples - Reference application to show how to use the driver APIs and calling sequence
|
- Source - Driver source files
HW/IP Features
Analog-to-Digital Converters
- Dual 12-bit 1 MSPS analog-to-digital converters (ADCs)
- Up to 17 flexible and user-configurable analog inputs
- On-chip or external reference option
- On-chip temperature and power supply sensors
- JTAG access to ADC measurements
PS-XADC Interface
- Read and write XADC registers
- Serial data transfers to/from XADC
- Buffered read-write data operations
- 15-word by 32-bit command FIFO
- 15-word by 32-bit
- Read Data FIFO
- Programmable FIFO-level interrupts
- Programmable alarm interrupts
- Configured interface operations (using devcfg registers)
- DRP Parallel Interface
- Highest interface bandwidth
- 6-bit sample data
PL-JTAG Interface
- Access the XADC when the PL is not programmed but is powered-up
- Uses the JTAG TAP controller to access the XADC registers
Test Cases
- xadcps_intr_example - This example shows the usage of the driver/device in interrupt mode to handle on-chip temperature and voltage alarm interrupts.
- xadcps_polled_printf_example - This example shows the driver/device in polled mode to check the on-chip temperature and voltages.
Changelog
2016.3
- None
2016.4
- None.
2017.1
- None
2017.2
- None
2017.3
- None.
2017.4
- None.
2018.1
- None.
2018.2
- None.
2018.3
- None
Related Links
- NA