Zynq UltraScale MPSoC Base TRD 2016.4 - Design Module 6

Return to the Design Tutorials Overview.



Design Overview


This module shows how to add a Test Pattern Generator (TPG) implemented in the PL.





Design Components


This module requires the following components:



Build Flow Tutorials


PL Base TRD


This tutorial shows how to build the Base TRD Vivado design that implements the TPG capture pipeline.


PMU Firmware


Please refer to design module 1 - PMU firmware for instructions or skip this step if you have built the PMU firmware in a previous module.

PetaLinux BSP


This tutorial shows how to build the Linux image and boot image using the PetaLinux build tool.


Video Qt Application


There is no need to rebuild the video_qt2 application if you have already built it in module 5, otherwise follow the instructions from module 5.




Run Flow Tutorial