Missing Features and known Issues/Limitations in Driver
None
Kernel Configuration
Xilinx Trafgen driver is not enabled in the current default kernel configuration. The following steps may be used to enable the driver in the kernel configuration
config XILINX_TRAFGEN
tristate "Xilinx Traffic Generator"
help
This option enables support for the Xilinx Traffic Generator driver.
It is designed to generate AXI4 traffic which can be used to stress
different modules/interconnect connected in the system. Different
configurable options which are provided through sysfs entries allow
allow the user to generate a wide variety of traffic based on their
their requirements.
If unsure, say N
Symbol: XILINX_TRAFGEN [=y]
Type : tristate
Prompt: Xilinx Traffic Generator
Location:
-> Device Drivers
-> Misc devices
Defined at drivers/misc/Kconfig:769 |
DevicetreeFor More details about the device-tree bindings please refer to the Documentation/devicetree/bindings/misc/xilinx-axitrafgen.txt file.
axi_traffic_gen_0: axi-traffic-gen@44a00000 {
compatible = "xlnx,axi-traffic-gen-2.0", "xlnx,axi-traffic-gen";
interrupt-names = "err-out", "irq-out";
interrupt-parent = <&axi_intc_0>;
interrupts = <0 2>, <1 2>;
reg = <0x44a00000 0x10000>;
xlnx,device-id = <0>;
} ; |
Test Procedure
Application for Advanced Mode or Basic Mode:
The application demonstrates by programming known data to Master RAM and commands to Command RAM. Initiating the master logic will take the data from Master RAM (from a location) and generate data for slave transactions which is directed to write into BRAM. And then write commands in Command RAM read the data from BRAM and write it back to Master RAM at a different location. The test passes when the master logic completes and verifies for data to same.
This example does mmap to Master RAM:atg_test.cThis example is based on h/w design with traffic generator connected to cores BRAM and DDR via an interconnect. This example tests the IP using BRAM, alternatively, you can use the DDR address map. If you are using DDR addresses ensure the address range is unmapped to the kernel.Also, modify the defines(PRAM_SYS_PATH, CRAM_SYS_PATH, MRAM_SYS_PATH, LAST_VALID_INDEX_PATH, START_MASTER_PATH, AXI_ADDRESS) in the examples according to your design.
Alternatlvely user can create bin files of their respective sizes (Master RAM -8K size) and then write directly to Master RAM from the linux prompt,Bin files can be easily created using open source 'hexedit' tool. An example usage case is provided below to test RAMs.$LINUX > cat 8K.bin > /sys/devices/axi.0/44a00000.axi-traffic-gen/driver/master_ram
/* Write to Master RAM */
$LINUX > cat /sys/devices/axi.0/trafgen0/44a00000.axi-traffic-gen/driver/master_ram > sri.bin /* Read from Master RAM */
$LINUX > diff 8K.bin sri.bin /* Compare both data */
$LINUX > hexdump -v -C sri.bin > temp.bin /* To see the contents of bin file */
BIN File:
NOTE: This example is based on h/w design with traffic generator connectedto cores BRAM and DDR via an interconnect. This example tests the IP using BRAM, alternatively you can use DDR address map. If you are using DDR addresses ensure the address range is unmapped to kernel.
Application for Streaming Mode:
This application demonstrates how to use the Streaming mode in the Axi traffic generator .In the Streaming mode the core generates Streaming traffic based
on the transfer length and transfer count configured.
Application:
NOTE: This example is based on h/w design with traffic generator connected to the axi Stream fifo.
Application for Static Mode:
This application demonstrates how to use the Static mode in the Axi traffic generator In static mode the core continuously generates fixed address and
fixed INCR type read and write transfers based on the burst length configured.
This example does mmap to the Bram memory inorder check the static mode
Application:
NOTE: This example is based on h/w design with traffic generator connected to cores BRAM and DDR via an interconnect. This example tests the IP using BRAM, alternatively you can use DDR address map. If you are using DDR addresses ensure the address range is unmapped to kernel.
Mainline Status
Not mainlinedChange Log