The Xilinx LogiCORE IP Zynq UltraScale+ RFSoC RF Data Converter IP core provides a configurable wrapper to allow the RF DAC and RF ADC blocks to be used in IP Integrator designs. Multiple tiles are available on each RFSoC and each tile can have a number of data converters (analog-to-digital (ADC) and digital-to-analog (DAC)). The RF ADCs can sample input frequencies up to 4 GHz at 4 GSPS with excellent noise spectral density. The RF DACs generate output carrier frequencies up to 4 GHz using the 2nd Nyquist zone with excellent noise spectral density at an update rate of 6.4 GSPS. The RF data converters also include power efficient digital down-converters (DDCs) and digital up-converters (DUCs) that include programmable interpolation and decimation, NCO and complex mixer. The DDCs and DUCs can also support dual-band operation.

Source path for the driver:

Driver source code is organized into different folders. Below diagram shows the rfdc driver source organization
-- Doc - Provides the API and data structure details
- Examples - Reference application to show how to use the driver APIs and calling sequence
- Source - Driver source files

RF-ADC Features

RF-DAC Features

Test Cases

For the RFSoC Data Converter, the interrupts are mostly used for error reporting.
The interrupts do not do any data processing. Since they don’t do any data processing, interrupts are invoked in rare conditions.
The example here attempts to demonstrate users how an error interrupt can be generated. Also once generated how does the processing happen. Upon an interrupt, the control reaches to ScuGIC interrupt handler. From there the control is transferred to the libmetal isr handling which then calls the driver interrupt handler. Users are expected to register their callbacks with the driver interrupt framework.
The actual interrupt handling is expected to happen in the user provided callback.
This example generates ADC fabric interrupts by writing some incorrect fabric data rate based on the read/write clocks.

This example does some writes to the hardware to do some sanity checks and does a reset to restore the original settings

This example uses multiple driver "set" APIs to configure the targeted AMS block. Subsequently it uses "get" APIs to read back the configurations to ensure that the desired configurations are applied.
For DAC it sets the following configurations:
MixerSettings, QMCSettings, Write Fabricrate, Decoder mode, Output Current and Coarse Delay.
For ADC it sets the following configurations:
MixerSettings, QMCSettings, Read Fabricrate and Threshold Settings.
This example shows how to change the configurations for ADC and DAC using driver functions.

This example test the Multi-Tile Sync feature and shows how to use the MTS APIs.








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