Zynq UltraScale+ MPSoC VCU TRD 2018.2


Table of Contents


1 Revision History

This wiki page complements the 2018.2 version of the VCU TRD.

Change Log:


2 Overview


The Zynq® UltraScale+™ MPSoC Video Codec Unit (VCU) Targeted Reference Design (TRD) consists of an embedded video encoding/decoding application that runs on the Processing System (PS). Overall functionality of the TRD is partitioned between the Processing System (PS), Video Codec Unit, and Programmable Logic (PL) for optimal performance. The below figure shows the TRD block diagram. It consists of four Design Modules (DM1, DM2, DM3, DM4). The components of each design module are highlighted in unique colors in the diagram. The remaining blocks are common to all design modules as shown.



The primary goal of this TRD is to demonstrate the capabilities of the VCU core which is an integrated hard block present in Zynq UltraScale+ MPSoC EV devices. The TRD serves as a platform for the user to tune the performance parameters of VCU and arrives at an optimal configuration for encoder and decoder blocks for their specific use case. The TRD uses Vivado IP Integrator (IPI) flow for building the hardware design and Xilinx Yocto PetaLinux flow for software design. It uses Xilinx IPs and software drivers to demonstrate the capabilities of different components. The TRD consists of four design-modules described in section 4.1.

The TRD supports the following video interfaces:

Sources:
Sinks:

This tutorial contains information about:

Additional material available for reference:


3 Software Tools and System Requirements


3.1 Hardware


Required:

Optional:

3.2 Software


Required:

3.3 Download, Installation, and Licensing


The Vivado Design Suite User Guide explains how to download and install the Vivado® Design Suite tools, which includes the Vivado Integrated Design Environment (IDE), High-Level Synthesis tool, and System Generator for DSP. This guide also provides the information about licensing and administering evaluation and full copies of Xilinx design tools and intellectual property (IP) products. The Vivado Design Suite can be downloaded from here.

LogiCORE IP Licensing

The following IP cores require a license to build the design.

To obtain the LogiCORE IP license, please visit the respective IP product page and get the license.

3.4 Compatibility


The reference design has been tested successfully with the following user-supplied components.

DisplayPort Monitor:
Make/ModelNative Resolution
Viewsonic VX2475SMHL-4K (VS16024)3840x2160 (30Hz)
LG 27MU67-B3840x2160 (30Hz)

HDMI Monitor:
Make/ModelResolutions
LG 27UD883840x2160 (30Hz)
Philips BDM4350UC3840 x 2160 @ 60Hz

HDMI Input Sources:

DisplayPort Cable:


4 Design Files


4.1 Design Modules


The TRD consists of four designs which are highlighted in four colors as shown in the above figure.

The following table shows the dependency matrix between different modules. For example: DM4 (row) depends on or builds on top of modules DM1.

ModuleDM1DM2DM3
DM1


DM2


DM3
+
DM4+


4.2 Download the TRD


The TRD has been tested on Rev B, Rev C, Rev D, Rev E, Rev F and Rev 1.0 ZCU106 evaluation boards with Production silicon. The following design files can be downloaded from here.

4.3 TRD Directory Structure and Package Contents


The TRD package is released with the source code, Vivado project, petalinux project, and SD card image that enables the user to run the demonstration. It also includes the binaries necessary to configure and boot the ZCU106 board. Prior to running the steps mentioned in this wiki page, download the TRD package and extract its contents to a directory referred to as ‘TRD_HOME' which is the home directory.





5 Tutorials

For the individual tutorials on each design module, follow the links below:

The table below lists the available hardware projects and the script used to generate them. These can be found in the scripts folder in package under "pl/scripts".
ModuleProject NameScript NameDescription
DM1HDMIRX + VCUhdmirx_proj.tclVCU based mini reference design showcasing HDMI receive along VCU capabilities of ZCU106 & MPSoC
DM2SDIRX + VCUsdirx_proj.tclVCU based mini reference design showcasing SDI receive and VCU capabilities of ZCU106 & MPSoC
DM3SDIRX + VCU + SDITXsdirxtx_proj.tclVCU based video design showcasing SDI receive and SDI transmit capabilities of ZCU106 board
DM4VCU TRDvcu_trd_proj.tclMulti stream VCU TRD design supporting 3 video pipelines (HDMI, TPG & MIPI)


6 Other Information


6.1 Known Issues


NOTE: TRD has been tested with normal latency mode and it's working fine. Reduced/sub_frame latency mode is disabled in GUI but, enabled in cmd line app for user experience.
NOTE: TRD has been tested with CBR rate control mode and it is working fine. VBR/low_latency rate control mode is disabled in GUI but, enabled in cmd line app for user experience.
$ killall -9 modetest
$ source /media/card/autostart.sh

6.2 Limitations



7 Support


To obtain technical support for this reference design, go to the: