Table of Contents
This wiki page complements the 2019.1 a version of the MPSoC VCU TRD.
This is the main page of VCU TRD wiki, which has links to redirect wiki pages corresponding to individual design modules. It also explains the complete feature list and the supported resources of all the designs. TRD package weblink is provided for the user to download. This page also gives information on required software tools, IP licenses.
The Zynq® UltraScale+™ MPSoC Video Codec Unit (VCU) Targeted Reference Design (TRD) consists of an embedded video encoding/decoding application that runs on the Processing System (PS). The overall functionality of the TRD is partitioned between the Processing System (PS), Video Codec Unit, and Programmable Logic (PL) for optimal performance.
The primary goal of this TRD is to demonstrate the capabilities of the VCU core which is an integrated hard block present in Zynq UltraScale+ MPSoC EV devices. The TRD serves as a platform for the user to tune the performance parameters of VCU and arrives at an optimal configuration for encoder and decoder blocks for their specific use case. The TRD uses Vivado IP Integrator (IPI) flow for building the hardware design and Xilinx Yocto PetaLinux flow for software design. It uses Xilinx IPs and software drivers to demonstrate the capabilities of different components
The TRD supports the following video interfaces:
Sources (up-to 4K-60FPS):
Sinks (up-to 4K-60FPS for HDMI and 4K-30FPS for Display Port):
Audio Codec :
The below figure shows the TRD block diagram. It consists of all the Design Modules. The components of each design module are highlighted in unique colors in the diagram. The remaining blocks are common to all design modules as shown.
The VCU TRD 2019.1 the version consists of eleven design-modules as described below. Individual links below will redirect to the corresponding wiki pages and build and run the flow of individual designs modules.
Design Module #
|1||VCU TRD||Multi-stream design supporting HDMI-Rx, TPG, MIPI, HDMI-Tx, DP along with showcasing capabilities of VCU.|
|2||SDI Capture and Display with Audio||Design showcasing Audio Video Capture and Display through SDI interface along with the capabilities of VCU|
|3||Multistream Audio||Design supporting I2S or HDMI Audio with video capture of HDMI-Rx/MIPI Rx and showcasing capabilities of VCU|
|4||10G Ethernet Video streaming||Design showcasing Video stream over 10G Ethernet along with the capabilities of VCU|
|5||HDMI Capture and Display with SDSoC accelerator|
Design showcasing PL based accelerator IP through SDSoC tool as post-processing plug-in for VCU
|6||PCIe transcode||Design to showcase file transfer from HOST(x86) machine over PCIe interface and transcode it on ZCU106 Board having VCU connected as PCIe endpoint and write back the transcoded data to the HOST machine.|
Design showcasing Video Capture through HDMI interface along with the capabilities of VCU
|8||HDMI Display||Design showcasing Video Display through HDMI interface along with the capabilities of VCU|
Design showcasing Video Capture only through SDI interface along with the capabilities of VCU
VCU based video design showcasing SDI transmit capabilities along with the capabilities of the VCU
|11||HDMI Capture and Display with PL DDR||This is the new design approach proposed to use PL DDR for decoding and PS DDR for encoding so that DDR bandwidth would be enough to support high bandwidth VCU applications requiring simultaneous encoder and decoder operations and transcoding at 4k@60fps.|
VCU TRD User guide has more details about the list of features, software architecture, and hardware architecture of individual designs. Here is the link for the user guide :
The Vivado Design Suite User Guide explains how to download and install the Vivado® Design Suite tools, which includes the Vivado Integrated Design Environment (IDE), High-Level Synthesis tool, and System Generator for DSP. This guide also provides information about licensing and administering evaluation and full copies of Xilinx design tools and intellectual property (IP) products. The Vivado Design Suite can be downloaded from here.
LogiCORE IP Licensing
The following IP cores require a license to build the design.
To obtain the LogiCORE IP license, please visit the respective IP product page and get the license.
The reference design has been tested successfully with the following user-supplied components.
Display Port Monitor:
|Viewsonic VX2475SMHL-4K (VS16024)||3840x2160 @ 30Hz|
|LG 27MU67-B||3840x2160 @ 30Hz|
|Dell-p2417h||1920x1080 @ 60Hz|
|LG 27UD88||3840x2160 @ 30Hz|
|Philips BDM4350UC||3840 x 2160 @ 60Hz|
|Dell-p2417h||1920x1080 @ 60Hz|
|BenQ - EW3270-T||3840 x 2160 @ 60Hz|
HDMI Input Sources:
The below section will provide the information on ZCU106 board setup for running TRD.
The above figure shows all the zcu106 board connections
The above figure shows all the zcu106 board connector slots
Determine which COM to use to access the USB serial port on the ZCU106 board.
Make sure that the ZCU106 board is powered on and a micro USB cable is connected between ZCU106 board and host PC. This ensures that the USB-to-serial bridge is enumerated by the PC host.
Open your computer's Control Panel by clicking on Start > Control Panel.
Note that the Start button is typically located in the lower left corner of the screen. Occasionally, it is in the upper left corner.
4. Note down the COM Port number for further steps.
5. Close the Device Manager by clicking the red X in the upper right corner of the window.
Launch any Terminal application like Tera term to view the serial messages
It boots Linux on board and It takes about a minute for Linux to boot.
The TRD supports Rev C, D, E, F and Rev 1.0 ZCU106 evaluation boards with Production silicon.
The TRD package is released with the source code, Vivado project creation scripts, Petalinux BSP, and SD card image that enables the user to run the demonstration. It also includes the binaries necessary to configure and boot the ZCU106 board. Prior to running the steps mentioned in this wiki page, download the TRD package and extract its contents to a directory referred to as ‘TRD_HOME' which is the home directory.
Below figure depicts the directory structure and the hierarchy of the TRD package :
The top-level directory structure is described below:
Refer to the individual wiki page links for known issues and limitation of that particular design.
To obtain technical support for this reference design, go to the: