Introduction
This page gives an overview of zdma driver which is available as part of the Xilinx Vivado and SDK distribution.ZDMA is a general purpose DMA designed to support memory to memory and memory to IO buffer transfers.
Zynq Ultrasclae+ MPSOC has two instance of general purpose ZDMA.
One is located in FPD (full power domain) which usually called as GDMA and other is located
in LPD (low power domain) which usually called as ADMA.
How to enable
Source path for the driver:https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/zdma
Driver source code is organized into different folders. Below diagram shows the zdma driver source organization
ZDMA
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-- Doc - Provides the API and data structure details
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- Examples - Reference application to show how to use the driver APIs and calling sequence
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- Source - Driver source files
Features Supported
Controller Features
- Configurable AXI bus width
- AXI 4 support , burst length is limited to 16 to provide AXI 3 compatibility
- SRC and DST payload can start and end at any alignment
- Over fetching can be enabled/disabled per channel
- Up to 8 configurable DMA channels
- Each channel can be programmed secure or non-secure
- Programmable number of outstanding transactions per channel
- Support for periodic transaction scheduling. Period can be independently programmed per channel
- Supports Simple(descriptor less) and Scatter Gather (SG) DMA modes
- Supports read only DMA mode
- Supports write only DMA mode
- Common Buffer is automatically shared among all enabled DMA channels
- Support for DMA START, STOP and PAUSE
- Interrupt Accounting support
- Descriptor prefetch support to maximize DMA efficiency
- Support for error recovery
- INCR & FIXED type burst supported
- Independent AXI burst length is supported on SRC & DST Side
- Support for per channel flow control interface
Standalone Driver Supported Features
The ZDMA Standalone driver support the below things.- GMDA & ADMA are configured each with 8 DMA channels and and each channel can be programmed secure or non-secure.
- It support two DMA Modes
- Simple DMA mode
- Normal data transfer from source to destination
- Write Only Mode
- Read Only Mode
- Scatter Gather DMA mode
- Normal data transfer from source to destination
- Simple DMA mode
- In Scatter gather Mode it supports 2 types of descriptors out of 3 that h/w supports
- Linear descriptor
- Linked list descriptor
- Interrupt Accounting Support
- INCR and Fixed burst are supported.
Test cases
- Refer below pah for testing differnet examples for each feature of the IP.
xzdma_selftest_example.c : – It includes few basic core API testing for self-test.
xzdma_writeonlymode_example.c - This is an example which explains how to use write only DMA feature
xzdma_readonlymode_example.c - This is an example which explains how to use read only DMA feature
xzdma_linear_example.c - This is an example which explains how to use Scatter Gather Linear descriptor mode.
xzdma_linkedlist_example.c - This is an example which explains how to use Scatter Gather Linked list descriptor mode.
xzdma_simple_example.c - This is an example which explains how to use simple DMA mode.
Known issues and Limitations
- Hybrid list descriptors are not supported.
- Flow controller feature is not supported
- Peripheral dma is not tested/supported.