Table of Contents

Introduction


The AXI USB device IP is an USB device controller IP. It has no support for OTG mode. This IP can be instantiated on FPGA or Zynq or ZynqMP PL. This page describes the usage of AXI USB device IP standalone driver.

How to Enable

Source Path for the driver:

https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/usb/

Driver source code is organized into different folders. Below diagram shows the usbpsu driver source organization

usb
|
-- Doc - Provides the API and data structure details
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- Examples - Reference application to show how to use the driver APIs and calling sequence
|
- Source - Driver source files

Features Supported

Controller Features Supported

Driver Features Supported


Known Issues and Limitations


Performance


Test Procedure

Mass storage profile can be tested by compiling files found in the below link

https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/usb/examples


Below is the testing procedure of AXI USB standalone example which operates as a mass storage gadget


Change Log

2017.3
Summary:

2017.4

2018.1

2018.2

2018.3

2019.1

2019.2

2020.1


2020.2