Boot Time From Dual Parallel QSPI

The goal is to be able to build a VCK190 design (QSPI dual Parallel) to reproduce the boot times outlined in the boot time estimator spreadsheet.

VCK190

https://github.com/Xilinx-Wiki-Projects/VCK190-Boot/tree/master/vck190_boot_time

2020.2

Fallback & Multiboot

Fallback boot allows Versal ACAP to automatically boot a different PDI than the initial PDI on the same primary boot device if the first PDI fails to boot.

VCK190

https://github.com/Xilinx-Wiki-Projects/VCK190-Boot/tree/master/vck190_fallback

2020.2

Post BootROM State

This Versal example design is intended to illustrate the post bootROM state (pre-PLM) of the device on different boot modes, just to verify the registers modified by Versal ROM code.

VCK190

https://github.com/Xilinx-Wiki-Projects/VCK190-Boot/tree/master/vck190_post_boot

2020.2

Boot Files

This blog post provides an overview of the Versal Boot files

Any

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/A-Brief-Overview-of-the-Versal-Boot-files/ba-p/1146981

2020.2

USB Secondary Boot Mode

In this blog entry we will demonstrate how to boot Linux from a USB secondary boot

VCK190

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/USB-secondary-boot-mode-testing-on-a-Versal-VCK190-Evaluation/ba-p/1186277

2020.2

JTAG Boot

Vivado in-depth tutorial covering the JTAG boot mode flow

VCK190

https://github.com/Xilinx/Vivado-Design-Tutorials/tree/master/Device_Architecture_Tutorials/Versal/Boot_and_Config/JTAG_Boot

2020.2

OSPI Boot

Example demonstrating octal SPI (OSPI) boot on a VCK190.

VCK190

https://github.com/Xilinx-Wiki-Projects/VCK190-Boot/tree/master/vck190_boot_ospi

2020.2

PDI Compression

This Versal example design will demonstrate how to generate a compressed and uncompressed PDI for the VCK190.

VCK190

https://github.com/Xilinx-Wiki-Projects/VCK190-Boot/tree/master/vck190_boot_compression

2020.2

AXI DMA

The Versal example design will show how to run AXI DMA standalone application example on VCK190 and intended to demonstrate the AXI DMA standalone driver which is available as part of the Xilinx Vivado and Vitis.

VCK190

https://github.com/Xilinx/XilinxCEDStore/tree/master/ced/Xilinx/IPI/VCK190-AXIDMA-Example

2020.2

CIPS and DDR

Configurable example design showing CIPS IP and DDR connections, delivered via the CED Store for use within Vivado

VCK190/VMK180

https://github.com/Xilinx/XilinxCEDStore/tree/master/ced/Xilinx/IPI/cips_ddr_pl_debug

2020.2

CIPS VIP

Configurable example design showing simulating with the CIPS Verification IP, delivered via the CED Store for use within Vivado

VCK190

https://github.com/Xilinx/XilinxCEDStore/tree/master/ced/Xilinx/IPI/cips_vip

2020.2

AXI BRAM

This Blog entry is intended to illustrate how to access the AXI BRAM from the Versal™ Application processing Unit (APU) through the NoC

VCK190

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Basic-read-write-to-AXI-BRAM-from-PS-APU-through-NoC-in-Versal/ba-p/1172775

2020.2

CIPS & MicroBlaze

This blog post shows how to leverage Versal CIPS IP from MicroBlaze

VCK190

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/How-to-leverage-Versal-CIPS-IP-from-MicroBlaze/ba-p/1184023

2020.2

Memory Interfaces

This blog entry will cover important information you should understand before designing with Memory Interfaces on Versal™ ACAP devices. 

Any

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Getting-Started-with-Versal-Memory-Interfaces/ba-p/1192335

2020.2

NoC and DDRMC

This example connects many different DDR devices simultaneously in one design to communicate to PS through NoC. It connects one DDR4 device and two interleaved LPDDR4 devices, which requires one NoC instance to configure the DDRMC for the DDR4 device and another NoC instance to configure the two interleaved DDRMCs for the two LPDDR4 devices.

VCK190/VMK180

https://github.com/Xilinx/Vivado-Design-Tutorials/tree/master/Device_Architecture_Tutorials/Versal/NoC_DDRMC/03-Multiple_DDRMC

2020.2

NoC and DDRMC

This tutorial introduces the basic concepts, tools, and techniques of the NoC and DDR memory controller design flow in Vivado

Any

https://github.com/Xilinx/Vivado-Design-Tutorials/blob/master/Device_Architecture_Tutorials/Versal/NoC_DDRMC/Intro_Design_Flow

2020.2

NoC and DDRMC

Learn how to tune your NoC and DDR memory controller designs to deliver optimum performance for your designs.

Any

https://github.com/Xilinx/Vivado-Design-Tutorials/blob/master/Device_Architecture_Tutorials/Versal/NoC_DDRMC/Performance_Tuning

2020.2

NoC

This tutorial uses a complex design example to demonstrate how the NoC simplifies the design process for on-chip data movement.

Any

https://github.com/Xilinx/Vivado-Design-Tutorials/blob/master/Device_Architecture_Tutorials/Versal/NoC_DDRMC/04-NoC_Data_Movement_Comparison

2020.2

PCB Design DDRMC

This tutorial introduces best pracices for working with DDR memory pinouts in Versal.

Any

https://github.com/Xilinx/Vivado-Design-Tutorials/blob/master/Device_Architecture_Tutorials/Versal/PCB_Design/Memory_Pinouts

2020.2

PCB Design DDR

This tutorial covers how to perform DDRx signal integrity simulations with the Mentor Graphics DDRx Wizard.

Any

https://github.com/Xilinx/Vivado-Design-Tutorials/blob/master/Device_Architecture_Tutorials/Versal/PCB_Design/Hyperlynx_DDRx_Timing_Models

2020.2

Versal Performance AXI Traffic Generator

The Performance AXI Traffic Generator is intended for modeling traffic masters in Versal™ ACAP designs for performance evaluation of network on chip (NoC) based solutions

VCK190

https://github.com/Xilinx/Vivado-Design-Tutorials/tree/master/Device_Architecture_Tutorials/Versal/NoC_DDRMC/Versal-Performance-Traffic-Generator

2020.2

DDR Calibration Done

This blog post shows how to export the DDR Calibration done pin to the PL in Versal.

Any

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Versal-How-to-export-the-DDR-Calibration-done-pin-to-the-PL/ba-p/1230598

2020.2

USB

Examples demonstrating Host & Device mode of the Versal PS USB controller.

VCK190

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/2069987899/Versal+Linux+USB+Device+Driver+Examples

2021.1

Low Speed Peripherals

This repository contains VCK190 design files for PS and PL based LowSpeed IPs.

There are few available designs:

• axi_can - AXI CAN IP design subsytem with CIPS

• axi_can_fd - AXI CAN FD design subsystem with CIPS

• axi_i2c - AXI IIC IP design subsytem with CIPS

• ps_i2c - PS IIC design only

• ps_can_fd - PS CAN FD design only

• axi_uartlite - AXI UARTLite IP design subsytem with CIPS

• ps_sbsa_uart - PS UART IP design only

VCK190

https://github.com/Xilinx/Embedded-Design-Tutorials/tree/master/examples/versal/lowspeed_IPs

2020.2

Advanced IO Wizard

This Blog entry is intended for new users of the Versal™ Advanced IO Wizard. It gives an introduction to setting up the Wizard and some insights into running a simulation. 

Any

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Versal-Advanced-IO-Wizard-Walk-through-on-using-the-Wizard-and/ba-p/1171904

2020.2

Multi-Rate GTY

This example describes a Versal GTY multi-rate design using the following configuration:

• Two rates: 10G and 25G switchable line rates

• Single GTY lane connected through SFP on VCK190/VMK180 evaluation board

VCK190/VMK180

https://github.com/Xilinx/XilinxCEDStore/tree/2020.2/ced/Xilinx/IPI/Versal%20Multi-Rate%20GTY

2020.2

Simplex TX/RX

This blog post shows how to combine Simplex TX/RX cores for several quads in IP Integrator

Any

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Versal-GTY-how-to-combine-Simplex-TX-RX-cores-for-several-quads/ba-p/1178478

2020.2

GTY Simulation

This blog entry covers a GTY simulation example, demonstrating how the GTY comes out of reset, and performs rate change.

Any

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Versal-GTY-Simulation-Initialization-Reset-and-Rate-Change/ba-p/1176867

2020.2

Combine Within GT Quad

This example introduces the design flow on combining different IP within one quad with the Xilinx Vivado Integrated Design Environment.

VCK190

https://github.com/Xilinx/XilinxCEDStore/tree/2020.2/ced/Xilinx/IPI/Versal%20Combine_within_GT_quad

2020.2

GTY and GTY/GTYP

This blog post discusses the differences between designing with UltraScale+ GTY and Versal GTY/GTYP

N/A

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Differences-Designing-with-UltraScale-GTY-and-Versal-GTY-GTYP/ba-p/1271972

N/A

PCIe Link Debug Demo

This Blog entry is shows how to debug the Versal ACAP Integrated Block for PCIe Express link issues using in-built "PCIe Link Debug" feature.

VCK190

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Debugging-Versal-ACAP-Integrated-Block-for-PCIe-Express-link/ba-p/1203707

2020.2

PS-GEM

This blog demonstrates how to bring up the PS-GEM in Versal.

VCK190

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Bringing-Up-a-1G-Ethernet-Interface-on-a-Versal-device/ba-p/1092703

2020.2

PS and PL based Ethernet

This GitHub repo contains design files demonstrating a PS 10/100/1000BASE-T design utilizing the GEM over MIO to the TI PHY onboard on the VCK190

VCK190

https://github.com/Xilinx-Wiki-Projects/VCK190-Ethernet

2020.2

PL 1G Ethernet

This project is about building Versal based AXI 1G/2.5G Ethernet Subsystem example design and testing it by targeting on VCK190 ACAP device using SGMII SFP

VCK190

https://github.com/Xilinx-Wiki-Projects/VCK190-Ethernet/tree/master/pl_eth_1G

2020.2

MRMAC

This blog covers the key differences between designing with UltraScale+ CMAC and Versal MRMAC.

Any

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Differences-between-Designing-with-UltraScale-CMAC-and-Versal/ba-p/1209580

2020.2

AI Engine tools, graphs, kernels and compiler

Series of blog posts that demonstrates how to get started with AI Engine tools, graphs, kernels and compiler.

VCK190

https://forums.xilinx.com/t5/AI-Engine-DSP-IP-and-Tools/Xilinx-Versal-AI-Engine-Series-Articles/td-p/1191630

2020.2

OpenAMP/FreeRTOS

This example demonstrates the usage of remoteproc kernel driver by the master processor (A72) on the VCK190 to load remote application firmware on the R5 processor.

VCK190

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/953647231/Loading+FreeRTOS+RPU+firmware+on+VCK190+using+remoteproc+driver

2021.1

Embedded Tutorial

The examples in this tutorial are created using the Xilinx tools running on a Windows 10, 64-bit operating system, Vitis software platform and PetaLinux on a Linux 64-bit operating system. Other versions of the tools running on other Windows installs might provide varied results. These examples focus on introducing you to the following aspects of embedded design.

VCK190

https://xilinx.github.io/Embedded-Design-Tutorials/master/docs/index.html

YouTube Videos:

1. https://www.youtube.com/watch?v=D-iUx3wxD5s&t=6s

2. https://www.youtube.com/watch?v=7iX44nWb9zA&t=2s

3. https://www.youtube.com/watch?v=GGJlAkVc9aw&t=3s

4. https://www.youtube.com/watch?v=drtAHHAcEyA&t=6s

5. https://www.youtube.com/watch?v=gdgfeOPTdfA