Introduction
The UART controller is a full-duplex asynchronous receiver and transmitter that supports a wide range of programmable baud rates. The server-based system applications (SBSA) functionality is defined by the Arm® architecture. There are two UART controllers, and they are located in the LPD IOP. The UART performs the following: • Serial-to-parallel conversion on data received from a peripheral device • Parallel-to-serial conversion on data transmitted to a peripheral device The software performs reads and writes of data and control/status information via the APB slave interface.
Driver Sources
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
Driver Name | Path in Vitis | Path in Github |
|---|---|---|
uartpsv | <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/uartpsv | https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/uartpsv |
Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/uartpsv
The driver source code is organized into different folders. The table below shows the uartpsv driver source organization.
Directory | Description |
|---|---|
doc | Provides the API and data structure details |
data | Driver .tcl and .mdd file |
examples | Example applications that show how to use the driver features |
src | Driver source files |
Driver Implementation
For a full list of features supported by this IP, please refer Versal TRM
Features
32 deep ×8-bit wide transmit FIFO
32 deep ×12-bit wide receive FIFO
Standard asynchronous communication bits (start, stop and parity)
Independent interrupt masking
Programmable hardware flow control
Fully-programmable serial interface characteristics
FIFO trigger levels selectable between 1/8, 1/4, 1/2, 3/4, and 7/8
Known Issues and Limitations
None
Example Applications
Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.
Links to Examples
Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/ospipsv/examples
Test Name | Example Source | Description |
|---|---|---|
Uartpsv interrupt example | This example sends and receives data using interrupts. | |
Uartpsv polled example | This example sends and receives data using polling. | |
Uartpsv hello world example | This example transmits “Hello world“ string |
Example Application Usage
Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.
Example Application Usage
Uartpsv interrupt example
This example sends and receives data using interrupts.
Expected Output
Successfully ran UartPsv Interrupt Example Test
Uartpsv polled example
This example sends and receives data using polling.
Expected Output
Successfully ran UartPsv Polling Example Test
Uartpsv hello world example
This example transmits “Hello world“ string
Expected Output
Successfully ran UartPsv Hello World Example
Example Design Architecture
NA
Change Log
2021.1
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L353
2020.2
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L353
2020.1
https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.1/doc/ChangeLog#L136
2019.2
None
2019.1
None