The purpose of this page is to give a high level overview of the Xen Hypervisor as it applies to Xilinx devices.
Table of Contents
Overview
Xen is a type-1 Hypervisor defined, maintained and provided to the open source community by the Xen Project. Xilinx actively contributes code to the Xen Project to provide Zynq UltraScale+ MPSoC platform support as well as key enhancements which benefit Xilinx customer use-cases.
Xen allows multiple instances of operating system(s) or bare-metal applications to execute on Zynq UltraScale+ MPSoC. Additional information on the Xen hypervisor can be found at the Xen Project Getting Started page.
Xilinx provides within the PetaLinux Tools and also in our Git tree, core elements and example designs to enable usage of Linux + bare-metal system configurations across the processing cores of Zynq UltraScale+ MPSoC. Key components of these example designs are described below in order to assist our customers to configure, build and deploy these basic configurations and to also identify current functionality gaps which may need to be further addressed within the customer's final system architecture.
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| One Linux DomU + two Bare-Metal Applications |
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| Linux Dom0 with custom apps + three Bare-Metal Applications |
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| Two Linux DomU + one Bare-Metal Application |
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| Three Linux DomU |
Xen-Based-System Feature Summary
Xilinx provides reference designs which include core capabilities for Xen-based systems. The table below lists important system features and their status under native Linux (no hypervisor), Linux Dom0 (on Xen), and Linux DomU (on Xen).Features that are not listed, or indicated as "Roadmap" below are not currently supported by Xilinx.
| Feature | Native Linux | Linux Dom0 | Linux DomU | Notes |
| Power Management – various functions | Yes | 2018.3 | 2018.3 | As of 2017.3, some functionality included in Xen Not fully featured or tested See Xen sources |
| FPGA_manager (write once) | Yes | Yes | Roadmap | See: FPGA Manager |
| FPGA_manager (write multiple) | 2018.1 | Target: 2018.1 | Roadmap | |
| Partial Reconfiguration | 2018.2 (non-secure) & 2018.3 (secure) . | Roadmap | Roadmap | |
| RPU life cycle management | Yes | Roadmap | Roadmap | |
| Device shared memory between DomU and RPU | Yes | 2018.1 | 2018.1 | |
| OpenAMP RPMsg comms APU/RPU | Yes | Roadmap | Roadmap | |
| Device shared memory DomU Linux to DomU Bare-metal | N/A | 2018.1 | 2018.1 | See: Xen Hypervisor Internals Xen Shared memory |
| Shared cacheable memory DomU to DomU | N/A | Roadmap | Roadmap | |
| GPU Usage | Yes | Roadmap | Roadmap | |
| PL IP Usage | Yes | Usable without limitation if the Xilinx AXI Sideband Format Utility IP is added to the design. Also usable without the AXI Sideband Format utility within the following conditions:
| Usable without limitation if the Xilinx AXI Sideband Format Utility IP is added to the design. Also usable without the AXI Sideband Format utility within the following conditions:
| See: Xen and PL Masters |
| PCIe Pass-through to DomU | N/A | Roadmap | Roadmap | |
| Warm Reset/Restart | Yes - under explicit use-cases | Roadmap | Roadmap | |
| Linux Application Debug | Yes (via TCF) | Yes (via JTAG) | Yes (via JTAG) | https://www.xilinx.com/html_docs/xilinx2017_3/SDK_Doc/SDK_concepts/concept_xen-aware_debug.html Build kernel with debug symbols enabled. |
| Bare-metal Xen Paravirtual Console | N/A | N/A | N/A - see note | Bare-metal DomU has access to Xen PV Console |
Using Xen Hypervisor with Xilinx Releases
- General information for configuring and Building Linux Dom0
- General information for configuring and Building Linux DomU
- Building a EL1 baremetal DomU guest with Xilinx SDK