2019.1 Release Notes for Open Source Components

Owned by Sandeep Gundlupet Raju
Last updated: Nov 24, 2020
5 min read

This page provides details on the 2019.1 release information such as new features and bug fixes for all the Xilinx Open Source Components. 

New Features

Note: Each "Component Name" has a link to respective pages. For more details refer individual pages.

Component Name
Platform/SoC Supported
Feature Description
Yocto
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Upgrade Yocto version to 2.6.1 Thud release
  • Added I2S audio feature support for Ultra96 V1 boards.
  • Added support for windowing like X11, FBdev and Wayland support in MALI user space libraries from Yocto using variable.
  • Support for evaluation boards like ZCU1285
FSBL or FS-Boot
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Added dual parallel configuration support and QPI support for 24bit  Macronix
  • AES engine and SHA engine are reset during FSBL initialization
  • Zeroize PL upon error in decryption
  • Remove sha2 support from FSBL
  • Always select EEPROM lower page for reading SPD data
  • Dynamic DDR configuration is strictly based upon the design for all boards
    ZCU102 and ZCU106 
  • Removed disabling of the WDT error before exiting FSBL to avoid overwriting of
  • Updated PMU with FSBL running status using bits 1 and 2 from PMU global
    5 general purpose register
  • Using XilPM XPm_SetConfiguration API instead of using direct IPI calls for
    PMUFW.communicatingwith
PMUFW (Platform Management Unit Firmware)
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Support APU-restart even when OCM is already consumed by Xilfpga
  • Update XilFPGA APIs to support
  • Add permission check for modifying error actions over IPI
  • Register handler and trigger FW error when Assert occurs
  • Add hook for custom module in PMU Firmware
  • Add handler for EMIO get reset status
  • Add PMU RAM ECC error injection STL during startup
  • Add check for number of users
  • Add support for Ultra96 power button
Arm Trusted Firmware (ATF)
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Upgrade ATF version to v20
  • Added support for new RFSoC detection ZU39DR.
  • Added checksum support for IPI messages in ZynqUS+ This can be enabled using build flag “ZYNQMP_IPI_CRC_CHECK”.
  • Added new API to get max supported clock divisor for a given clock id.
  • Fixed issue setting up DIV1 for GEM
  • Added new API GET_CALLBACK_DATA to read back data from IPI.
  • Fix WDT issue in kernel by adding LPD WDT to clock list and removing it from invalid
  • Rename WDT clock id to FPD_WDT to avoid confusion with LPD WDT.
  • Refactor/ move the code around for reusing the same for Versal platform.
U-boot
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Upgrade to upstream version v201901
  • Multi-Master I2C support
  • SHA and RSA operations support
  • USB3.0 driver
  • Added support for ISSI flash devices IS25LP128F IS25WP128F, IS25LP256D IS25WP256D IS25LP512M and IS25WP512M
Device-tree Generation (DTG)
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Team Block DesignProductize
  • Added support for memory based scene change detector
  • Added support for Ethernetugxsgmii
  • Added IP support in DTGapmps
  • Added support for custom overlay
Linux Kernel and Drivers
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Upgrade to v4.19 version
  • WWDT Driver support
  • Secure partition load from Linux
  • Mid density ISSI serial NOR flash support  - Added support for ISSI flash devices IS25LP128F, IS25WP128F, IS25LP256D, IS24WP256D, IS25LP512M AND IS25WP512M
  • Uartlite clock adaptation
OpenAMP and Libmetal
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • None
VCU (Video Codec Unit)
  • Zynq UltraScale+ MPSoC
  • Dynamic Resolution Change
    1. VCU Decoder and Encoder support at Control-software
  • Frame skipping support for VCU encoder rate-control
  • Full support for PL DDR
  • Rate control: Capped VBR
  • SEI NAL Unit insertion at Gstreamer Level
  • DCI 4K (4096x2160 @60fps support
  • VCU Encoder – VQ improvement options
    1. Temporal layer ID support for Pyramidal GOP
    2. on temporal layer
    3. Lambda Table update based on temporal layer
  • 32 streams - 420P (Encode and Decode)
  • Adaptive GOP Support (Ability to change number of dynamically)
  • VCU PL DDR Controller support for Limited DRAM parts
  • Audio Video Multistream feature use case.
QEMU
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • None.
Xen
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Added Shared Memory between Linux and Bare-metal guests.
  • Improved Xen + Dom0 in faster DomU start-up
  • Incorporate clock control for EEMI calls from Xen Dom
  • Linux DomU Power Management Access
BSP, Drivers and Libraries
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Added options to enable/ FreeRTOS10.0.0 new features "Message Buffers" and "Stream Buffers"
  • XILFPGA: Optimize the delays in the PS-PL resets path.

  • XILFPGA: Optimize the execution time for Image validation.

  • XILFPGA: Remove redundant API's from the interface agnostic layer and make the existing API's generic.

  • XILFPGA: Optimize the validation logic for Non-secure Images.

  • XILFPGA: Added CSUDMA address alignment check.

  • XILSECURE: Refactor/ move the code around for reusing the code for Versal platform.
  • XILSECURE: RSA Private Key Zeroization in RSA Core
  • XILSECURE: Deprecated SHA2 support
  • XILSECURE: Deprecated XSecure_RsaDecrypt call, updated with XSecure_RsaPublicEncrypt)
  • XILSKEY: Removed PPK0/1 SHA2 hash programming support
  • XILSKEY: Added example for PUF regeneration.
  • XILSKEY: Added support for SSIT devices on
  • Support for mid-density ISSI serial NOR flash for SoCs, MPSoCs, and RFSoCs - XILSF
  • XilPM: Added checksum support for IPI messages
  • XilPM: Added support for IAR compiler
  • XilPM: Updated example code to be compatible with IAR compiler
  • XilPM: Deprecated PM_SECURE_RSA_AES
  • XilPM: Added support for compiler

Bug Fixes

Note: Each "Component Name" has a link to respective pages. For more details refer individual pages.

Component Name
Platform/SoC Supported
Bug Description
Yocto
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Fixed warnings for browser-layer in Yocto 2.6.1 Thud release
  • Fixed "INIT: Id "X0" respawning too fast: disabled for 5 minutes" messages for ZynqMP devices in meta-virtualization layers
  • Fixed warnings for when is enabled as in DISTRO_FEATURES
  • Fix for kernel config CONFIG_XEN_NETDEV_FRONTEND as module
FSBL or FS-Boot
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • None
PMUFW (Platform Management Unit Firmware)
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Idle nodes only once even if they are assigned to multiple masters
  • Add support to idle and reset all twelve TTCs
  • Fix CRC checksum related issues in IPI messaging
  • nodes to handle the states of PP0 and PP1
  • Bypass DDR related code if DDR is not present in the design
  • Check for parent node in PmSlaveGetWakeUpLatency to avoid access to invalid memory
  • Check for NULL before calling get reset status operations to avoid access to invalid memory
  • Leave MIO34 and connect to PMU GPO only when it need to be driven low when configures through macros
  • Handle PLL lock errors during PLL reset
  • Remove APU access to LPD WDT clock register over MMIO read/write
  • Fix DDR_reinit incorrectly checks for PLL lock on unused PLLs
Arm Trusted Firmware (ATF)
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • None
U-boot
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Fixed loading error values in hexadecimal
  • Fixed prioritizing external if itspassed via EXT_DTB than the that was in the tree
  • Fixed for post configuration error messages
Device-tree Generation (DTG)
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Fixed other topology values defined for SCALAR and CSC
  • Fixed clock frequency type with floating point values
  • Fixed error messages in SDI RX IP for MicroBlaze design
  • Fixed HDMI RX - reference issue
Linux Kernel and Drivers
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Fixed runtime power management for drivers
  • Fixed DP to HDMI adapter training issue in newer DRM framework
  • Added a fix for i2c cadence in the  interrupt flurry case. 
  • Fixed intermittent RSA crash
  • driver - Increased sub resolution, Fixed driver to use RXUBR reset workaround only on devices, added null checks for mandatory clocks, mainline fixes for random RX memory corruption and race on 64 bit systems. 
  • CAN/CANFD driver - Fixed FSR register handling in path and data logic for CANFD frames.
  • QSPI driver - Fixed incorrect tap delay settings for different frequencies
  • uartps : Add support for cts-override
  • i2c: : Make the start and the byte count write atomic
  • usb: Fixed BUS Expiries occurring for Isochronous transfers when using USB Video Class
OpenAMP and Libmetal
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Fixed for -proxy-module is no longer required for application in UG1186 documentation
  • Fixed for rpmsg_user_dev_driver module is no longer required in UG1186
VCU (Video Codec Unit)
  • Zynq UltraScale+ MPSoC
  • Fixed issue with encode -stream based on available cores and other resources
  • Fixed VCU control software decoder example application issue while decoding streams with errors
QEMU
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Fixed incorrect DDR Bank 2 size 
Xen
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Fixed Ethernet, SD APM, WDT, UART, GPIO and other driver probe failures during Xen dom0 boot up
BSP, Drivers and Libraries
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Added SD UHS modes support for Microblaze Platform
  • Fixed Cache Invalidation issue in SD driver.
  • Fixed memory leak issue in Zynq QSPI driver
  • Added a dummy READ ID support when startup block is enabled in AXI QSPI driver

  • XILFPGA: Fixed PL power-up issue with pmufw.

  • XILFPGA: Fix safety issues with xilfpga functions return status.

  • XILFPGA: Fix IAR compilation issue for xilfpga library.

  • XILFPGA: Removed SecureIV shared variable dependency and updated the secure Iv handling logic.

  • XILFPGA: Fixed MISRA-C violations.

  • XILSECURE: Fixed Zeroization issue in case of AES decryption failure.
  • XILSECURE: Added state machines and timeouts the library for RSA, AES and SHA.
  • XILSECURE: Held Crypto engines (SHA, AES and RSA) under reset after use. 
  • XILSECURE: Added IAR Compiler support.
  • XILSKEY: Added GPIO selection based on the design for Microblaze.
  • XilPM: Remove and library dependencies
  • XilPM: Misra C fixes

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