AXI DMA Standalone Driver

AXI DMA Standalone Driver

Introduction
This page gives an overview of axi dma driver which is available as part of the Xilinx Vivado and SDK distribution. The Xilinx® LogiCORE™ IP AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core for use with the Xilinx Vivado® Design Suite. The AXI DMA provides high-bandwidth direct memory access between memory and AXI4-Stream target peripherals. Its optional scatter/gather capabilities also offload data movement tasks from the Central Processing Unit (CPU).

How to enable

Source Path for the driver
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/axidma

Driver source code is organized into different folders. Below diagram shows the axidma driver source organization

AXI DMA
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-- doc - Provides the API and data structure details
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-- data- Driver tcl and MDD file.
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- examples - Reference application to show how to use the driver APIs and calling sequence
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- src- Driver source files

Features Supported

Controller Features

• AXI4 compliant
• Optional Scatter/Gather Direct Memory Access (DMA) support
• AXI4 data width support of 32, 64, 128, 256,512 and 1,024 bits
• AXI4-Stream data width support of 8, 16, 32, 64, 128, 256, 512 and 1,024 bits
• Supports multichannel operation (up to 16 channels)
• Supports two-dimensional (2-D) transfers in multichannel mode.
• Optional Keyhole support
• Optional Data Re-Alignment support
• Optional AXI Control and Status Streams
• Optional Micro DMA Support
• Support for up to 64-bit addressing
• Support for Cyclic DMA Mode

Standalone Driver Supported Features

The AXI DMA Standalone driver supports the below things.

• Supports Simple DMA mode
• Supports Scatter/Gather Direct Memory Access (DMA)
• Support multi-channel operation (up to 16 channels)
• Supports 64-bit Addressing
• Supports Key Hole Feature
• Supports Optional Data Re-Alignment Feature

Test cases

• Refer below pah for testing different examples for each feature of the IP.

https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/axidma/examples

xaxidma_example_selftest.c : This example does a basic reset of the core and checks core is coming out of reset or not.
xaxidma_example_sg_intr.c : This example demonstrates how to transfer packets in interrupt mode when the core is configured in Scatter Gather Mode.
xaxidma_example_sg_poll.c : This example demonstrates how to transfer packets in the scatter gather polled mode.
xaxidma_example_simple_intr.c : This example demonstrates how to transfer packets in interrupt mode when the core is configured in Simple DMA Mode.
xaxidma_example_simple_poll.c : This example demonstrates how to transfer packets in the polled mode when the core is configured in Simple DMA Mode.
xaxidma_multichan_sg_intr.c : This example demonstrates how to packets in interrupt mode when the core is configured in Multi-Channel Mode.
xaxidma_poll_multi_pkts.c : This example demonstrates how to transfer multiple packets in the polled mode when the core is configured in Scatter Gather Mode.

Known issues and Limitations

• When H/w is configured without DRE driver will throw an error if the user sends an unaligned address.
• User application should handle buffer address alignment in case h/w is configured without DRE.

Change Log

2020.1

• Fix test failure with smaller packet size
• Clean up old versions for axidma driver
• Removed deprecated xaxidma_example_multichan_sg_intr.c

932b059 examples: Fix test failure with smaller packet size 
783bcfb axidma: Clean up old versions for axidma driver
b563c20 axidma: Removed deprecated xaxidma_example_multichan_sg_intr.c

c4e6089 axidma: examples: Fix test completion check in sgcyclic example
79443aa axidma: Fix XAxiDma_BdRingFromHw implementation for cyclic mode
de4ca5f axidma: examples: Fix use of elif check in deriving DDR_BASE_addr

2018.2

• Add support for 64MB data transfer.

Commit Id's:
31e7269axidma: Add support for 64MB data transfer
2018.1

• Fix multichan_sg_intr example on a53.
• Use UINTPTR type for storing address.
• Use virtual addr for BD access in _UpdateBdRingCDesc().
• Extend AXI DMA examples to support data buffers above 4GB.

Commit Id's:
99daacd axidma: multichan_sg_intr example fails on a53
3b16fc4 axidma: Use UINTPTR type for storing address
22fccbd axidma: Use virtual addr for BD access in _UpdateBdRingCDesc()
52642da axidma: Extend AXI DMA examples to support data buffers above 4GB
2017.4

• Fixed issue poll_multi_pkt example fails on a53.
• Fixed bug in the XAxiDma_Reset() API
• Added interface to lookup XAxiDma_Config based on base address

Commit Id's:
ea6a32e: Fix issue poll_multi_pkt example fails on a53
b863c69: Fix bug in the XAxiDma_Reset() API
da7ec38: Add interface to lookup XAxiDma_Config based on base address
2017.3

• Add support for cyclic DMA mode
• Rename the example files to select individual examples

Commit Id's:
d306b2b: axidma: Add support for cyclic DMA mode
b5a9fce : axidma: Rename the example files to select individual examples
2017.2

• None

2017.1

• None

Related Links

• http://www.wiki.xilinx.com/Baremetal+Drivers+and+Libraries