Title: Zynq UltraScale+ MPSoC VCU TRD 2020.2  
Owner: Ronak Shah
Creator: Ronak Shah Nov 05, 2020
Last Changed by: Gaja Lakshmi R Nov 27, 2020
Tiny Link: (useful for email) https://xilinx-wiki.atlassian.net/wiki/x/RAA4P
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Xilinx Wiki (1)
    Page: ZCU106 VCU Reference Design for QNX - 2020.2
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Children (13)
    Page: Zynq UltraScale+ MPSoC VCU TRD 2020.2 - Run and Build Flow
    Page: Zynq UltraScale+ MPSoC VCU TRD 2020.2 - VCU TRD Multi Stream Video Capture and Display
    Page: Zynq UltraScale+ MPSoC VCU TRD 2020.2 - PL DDR SDI Audio Video Capture and Display
    Page: Zynq UltraScale+ MPSoC VCU TRD 2020.2 - Multi Stream Audio Video Capture and Display
    Page: Zynq UltraScale+ MPSoC VCU TRD 2020.2 - 10G HDMI Video Capture and Display
    Page: Zynq UltraScale+ MPSoC VCU TRD 2020.2 - PCIe
    Page: Zynq UltraScale+ MPSoC VCU TRD 2020.2 - PL DDR HDR10 HDMI Video Capture and Display
    Page: Zynq UltraScale+ MPSoC VCU TRD 2020.2 - Xilinx Low Latency PS DDR NV12 HDMI Audio Video Capture and Display
    Page: Zynq UltraScale+ MPSoC VCU TRD 2020.2 - Xilinx Low Latency PL DDR NV16 HDMI Video Capture and Display
    Page: Zynq UltraScale+ MPSoC VCU TRD 2020.2 - Xilinx Low Latency PL DDR XV20 HDMI Video Capture and Display
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Time Editor  
Nov 27, 2020 09:07 Gaja Lakshmi R View Changes
Nov 27, 2020 08:56 Gaja Lakshmi R View Changes
Nov 27, 2020 08:23 Gaja Lakshmi R View Changes
Nov 26, 2020 08:09 Ronak Shah View Changes
Nov 25, 2020 10:51 Ronak Shah  
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Xilinx Wiki (2)     Page: Zynq UltraScale+ MPSoC VCU TRD 2020.2
    Page: Zynq UltraScale+ MPSoC VCU TRD 2020.1