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Code Block
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : @STACK_SIZE@;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : @HEAP_SIZE@;

_EL0_STACK_SIZE = DEFINED(_EL0_STACK_SIZE) ? _EL0_STACK_SIZE : 1024;
_EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 2048;
_EL2_STACK_SIZE = DEFINED(_EL2_STACK_SIZE) ? _EL2_STACK_SIZE : 1024;

@MEMORY_SECTION@

/* Specify the default entry point to the program */

ENTRY(_vector_table)

/* Define the sections, and where they are mapped in memory */

SECTIONS
{
.text : {
   KEEP (*(.vectors))
   *(.boot)
   *(.text)
   *(.text.*)
   *(.gnu.linkonce.t.*)
   *(.plt)
   *(.gnu_warning)
   *(.gcc_execpt_table)
   *(.glue_7)
   *(.glue_7t)
   *(.ARM.extab)
   *(.gnu.linkonce.armextab.*)
} > @DDR@

.init (ALIGN(64)) : {
   KEEP (*(.init))
} > @DDR@

.fini (ALIGN(64)) : {
   KEEP (*(.fini))
} > @DDR@

.interp : {
   KEEP (*(.interp))
} > @DDR@

.note-ABI-tag : {
   KEEP (*(.note-ABI-tag))
} > @DDR@

.rodata : {
   . = ALIGN(64);
   __rodata_start = .;
   *(.rodata)
   *(.rodata.*)
   *(.gnu.linkonce.r.*)
   __rodata_end = .;
} > @DDR@

.rodata1 : {
   . = ALIGN(64);
   __rodata1_start = .;
   *(.rodata1)
   *(.rodata1.*)
   __rodata1_end = .;
} > @DDR@

.sdata2 : {
   . = ALIGN(64);
   __sdata2_start = .;
   *(.sdata2)
   *(.sdata2.*)
   *(.gnu.linkonce.s2.*)
   __sdata2_end = .;
} > @DDR@

.sbss2 : {
   . = ALIGN(64);
   __sbss2_start = .;
   *(.sbss2)
   *(.sbss2.*)
   *(.gnu.linkonce.sb2.*)
   __sbss2_end = .;
} > @DDR@

.data : {
   . = ALIGN(64);
   __data_start = .;
   *(.data)
   *(.data.*)
   *(.gnu.linkonce.d.*)
   *(.jcr)
   *(.got)
   *(.got.plt)
   __data_end = .;
} > @DDR@

.data1 : {
   . = ALIGN(64);
   __data1_start = .;
   *(.data1)
   *(.data1.*)
   __data1_end = .;
} > @DDR@

.got : {
   *(.got)
} > @DDR@

.got1 : {
   *(.got1)
} > @DDR@

.got2 : {
   *(.got2)
} > @DDR@

.ctors : {
   . = ALIGN(64);
   __CTOR_LIST__ = .;
   ___CTORS_LIST___ = .;
   KEEP (*crtbegin.o(.ctors))
   KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
   KEEP (*(SORT(.ctors.*)))
   KEEP (*(.ctors))
   __CTOR_END__ = .;
   ___CTORS_END___ = .;
} > @DDR@

.dtors : {
   . = ALIGN(64);
   __DTOR_LIST__ = .;
   ___DTORS_LIST___ = .;
   KEEP (*crtbegin.o(.dtors))
   KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
   KEEP (*(SORT(.dtors.*)))
   KEEP (*(.dtors))
   __DTOR_END__ = .;
   ___DTORS_END___ = .;
} > @DDR@

.fixup : {
   __fixup_start = .;
   *(.fixup)
   __fixup_end = .;
} > @DDR@

.eh_frame : {
   *(.eh_frame)
} > @DDR@

.eh_framehdr : {
   __eh_framehdr_start = .;
   *(.eh_framehdr)
   __eh_framehdr_end = .;
} > @DDR@

.gcc_except_table : {
   *(.gcc_except_table)
} > @DDR@

.mmu_tbl0 (ALIGN(4096)) : {
   __mmu_tbl0_start = .;
   *(.mmu_tbl0)
   __mmu_tbl0_end = .;
} > @DDR@

.mmu_tbl1 (ALIGN(4096)) : {
   __mmu_tbl1_start = .;
   *(.mmu_tbl1)
   __mmu_tbl1_end = .;
} > @DDR@

.mmu_tbl2 (ALIGN(4096)) : {
   __mmu_tbl2_start = .;
   *(.mmu_tbl2)
   __mmu_tbl2_end = .;
} > @DDR@

.ARM.exidx : {
   __exidx_start = .;
   *(.ARM.exidx*)
   *(.gnu.linkonce.armexidix.*.*)
   __exidx_end = .;
} > @DDR@

.preinit_array : {
   . = ALIGN(64);
   __preinit_array_start = .;
   KEEP (*(SORT(.preinit_array.*)))
   KEEP (*(.preinit_array))
   __preinit_array_end = .;
} > @DDR@

.init_array : {
   . = ALIGN(64);
   __init_array_start = .;
   KEEP (*(SORT(.init_array.*)))
   KEEP (*(.init_array))
   __init_array_end = .;
} > @DDR@

.fini_array : {
   . = ALIGN(64);
   __fini_array_start = .;
   KEEP (*(SORT(.fini_array.*)))
   KEEP (*(.fini_array))
   __fini_array_end = .;
} > @DDR@

.drvcfg_sec : {
    . = ALIGN(8);
     __drvcfgsecdata_start = .;
    KEEP (*(.drvcfg_sec))
    __drvcfgsecdata_end = .;
    __drvcfgsecdata_size = __drvcfgsecdata_end - __drvcfgsecdata_start;
} > @DDR@

.ARM.attributes : {
   __ARM.attributes_start = .;
   *(.ARM.attributes)
   __ARM.attributes_end = .;
} > @DDR@

.sdata : {
   . = ALIGN(64);
   __sdata_start = .;
   *(.sdata)
   *(.sdata.*)
   *(.gnu.linkonce.s.*)
   __sdata_end = .;
} > @DDR@

.sbss (NOLOAD) : {
   . = ALIGN(64);
   __sbss_start = .;
   *(.sbss)
   *(.sbss.*)
   *(.gnu.linkonce.sb.*)
   . = ALIGN(64);
   __sbss_end = .;
} > @DDR@

.tdata : {
   . = ALIGN(64);
   __tdata_start = .;
   *(.tdata)
   *(.tdata.*)
   *(.gnu.linkonce.td.*)
   __tdata_end = .;
} > @DDR@

.tbss : {
   . = ALIGN(64);
   __tbss_start = .;
   *(.tbss)
   *(.tbss.*)
   *(.gnu.linkonce.tb.*)
   __tbss_end = .;
} > @DDR@

.bss (NOLOAD) : {
   . = ALIGN(64);
   __bss_start__ = .;
   *(.bss)
   *(.bss.*)
   *(.gnu.linkonce.b.*)
   *(COMMON)
   . = ALIGN(64);
   __bss_end__ = .;
} > @DDR@

_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );

_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );

/* Generate Stack and Heap definitions */

.heap (NOLOAD) : {
   . = ALIGN(64);
   _heap = .;
   HeapBase = .;
   _heap_start = .;
   . += _HEAP_SIZE;
   _heap_end = .;
   HeapLimit = .;
} > @DDR@

.stack (NOLOAD) : {
   . = ALIGN(64);
   _el3_stack_end = .;
   . += _STACK_SIZE;
   __el3_stack = .;
   _el2_stack_end = .;
   . += _EL2_STACK_SIZE;
   . = ALIGN(64);
   __el2_stack = .;
   _el1_stack_end = .;
   . += _EL1_STACK_SIZE;
   . = ALIGN(64);
   __el1_stack = .;
   _el0_stack_end = .;
   . += _EL0_STACK_SIZE;
   . = ALIGN(64);
   __el0_stack = .;
} > @DDR@


_end = .;
}

Known Gaps (

...

2024.1)

Generic Workflow Gaps

Baremetal/RTOS

Missing Support

Support for armclang, armcc and IAR compilers.

Few Kria SOM specific applications like Image Selector and Image Recovery are not yet ported.

Support for XilPKI library

Support for ZynqUS+ A53 32-bit

Support for Libmetal and OpenAM FreeRTOS apps

Support of OpenAMP for Zynq Cortex-A9 and Versal, ZU+ R5_1 processsors

Missing Features

Some of the standalone BSP configurations 

Each TTC timer is supposed to have three timer instances. This flow is treating them as a single instance.

The last two timer instances for each timer are not available for use.

Running the peripheral test with UART tests included may lead to junk characters on console for UART specific tests.

Linux

Missing Support

User may see some extra IP related properties (not available in the respective linux dt-binding) within the device node in the Lopper generated Linux device tree.

Support for Linux Device tree generation for Microblaze, Microblaze RISC-V and Zynq platforms.

Only supports ZynqMP and Versal (or Versal-like) platforms.

Support for Linux use cases of Video IPs.

Device nodes generated for Video IPs are not compatible with existing Linux bindings.

Support for Linux AIE drivers

Support for XRT and ZOCL

Isolation

Missing Support

Isolation support for ZynqMP platforms. Only supports Versal platforms.

SDTGen Specific Gaps

Overall

Missing Support

Support for HBM memory

Vitis Unified specific Gaps

Baremetal/RTOS

Missing Support

The AMD Vitis™ unified software still takes design file (.xsa) as an user input for some of the debugging purposes.

It internally converts the .xsa into system device tree and use the generated SDT directory for rest of the build flow.

Linux

Missing Support

Support for Linux Device Tree generation through UI

Petalinux/Yocto specific Gaps

Linux

Missing Support

Linux support for Microblaze, Zynq. Only supports ZynqMP and Versal (or Versal-like) platforms.

Vivado Specific Gaps

Baremetal

Missing Support

Vivado generates PLM which is part of the exported hardware platform in the form of a PDI for versal/versal-like platforms.

These are still generated using the Legacy flow.

Known

...

Gaps (

...

2023.2)

  1. Incremental Build for the BSP and the application is not yet available. In case of any source change in BSP, the whole BSP has to be compiled again and the same goes for the application workspace.

  2. Hardware related errors for a template application or a library have to be explicitly added via cmake files. Earlier it was handled in tcl but the same is not translated to yaml.

  3. The BSP workspace and the Application Workspaces are not completely relocatable. Build folders (for BSP, it is <bsp_ws>/libsrc/build_configs and for application, it is <app_ws>/build) have to be deleted before relocating.

  4. All the microblaze designs are expected to have "microblaze" in their processor names. This issue will be resolved in the coming release.

  5. In case of Embeddedsw repo having the multiple versions of the same component (say csudma_v3_5 and csudma_v3_6 as it used to be in the legacy flow), the build system will pick the first source sequenced alphabetically by default (csudma_v3_5 in this case). The source can later be changed (csudma_v_6 path can be chosen among the available options) once the BSP is created.

  6. Not all drivers/libraries/apps/examples in embeddedsw are ported to this new flow. Incase if a driver/library/app isnt ported, it wouldn't be considered while creating BSP/application and the example wouldnt showup for selection in GUI.

  7. IAR/armcc compilers are not supported

  8. ZynqUS+ A53 32-bit is not supported

  9. 64 bit Soft Microblaze is not supported

  10. Few of the BSP/Library configuration settings have been relocated and some of them have been removed during this transition to new SDT based flow.

  11. Libmetal and OpenAM FreeRTOS apps arent supported yet and support of OpenAMP for Zynq Cortex-A9 and Versal, ZU+ R5_1 processsors isnt present yet in this new flow

  12. STDIN and STDOUT configuration selection for FreeRTOS BSP isnt present.

  13. Memory region names are slightly modified in the linker script from the legacy flow. Linear_qspi/EMC memories are currently missing in the linker script.

  14. LwIP library can't be added to a FreeRTOS platform BSP settings. Workaround is to create a FreeRTOS lwIP template application and place the files needed for the custom application in the source folder. Default lwIP FreeRTOS apps work as expected and are unaffected by this issue.

...