Multi-Rate GTY

This example describes a Versal GTY multi-rate design using the following configuration:

• Two rates: 10G and 25G switchable line rates

• Single GTY lane connected through SFP on VCK190/VMK180 evaluation board

VCK190/VMK180

https://github.com/Xilinx/XilinxCEDStore/tree/2020.2/ced/Xilinx/IPI/Versal%20Multi-Rate%20GTY

2020.2

Simplex TX/RX

This blog post shows how to combine Simplex TX/RX cores for several quads in IP Integrator

Any

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Versal-GTY-how-to-combine-Simplex-TX-RX-cores-for-several-quads/ba-p/1178478

2020.2

GTY Simulation

This blog entry covers a GTY simulation example, demonstrating how the GTY comes out of reset, and performs rate change.

Any

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Versal-GTY-Simulation-Initialization-Reset-and-Rate-Change/ba-p/1176867

2020.2

Combine Within GT Quad

This example introduces the design flow on combining different IP within one quad with the Xilinx Vivado Integrated Design Environment.

VCK190

https://github.com/Xilinx/XilinxCEDStore/tree/2020.2/ced/Xilinx/IPI/Versal%20Combine_within_GT_quad

2020.2

GTY and GTY/GTYP

This blog post discusses the differences between designing with UltraScale+ GTY and Versal GTY/GTYP

N/A

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Differences-Designing-with-UltraScale-GTY-and-Versal-GTY-GTYP/ba-p/1271972

N/A