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The MIPI CSI-2 RX subsystem allows you to quickly create systems based on the MIPI protocol. It interfaces between MIPI-based image sensors and an image sensor pipe. An internal high speed physical layer design, D-PHY, is provided that allows direct connection to image sources.
IP/Driver Features
| IP Features | 2018.1 | 2018.2 | 2018.3 | 2019.1 | 2019.2 | 2020.1 | 2020.2 |
|---|---|---|---|---|---|---|---|
| IP version | 3.0 | 3.0 | 4.0 | 4.0 | 4.1 | 5.0 | |
| Support for 1 to 4 D-PHY lanes | NA | ||||||
| Line rates ranging from 80 to 1500 Mb/s | NA | ||||||
| Multiple Data Type support (RAW, RGB, YUV) | IP allows RAW6/7/8/10/12/14, all RGB and YUV 422 8bpc Driver allows to set any format except when RAW10 and RAW12. | IP allows RAW6/7/8/10/12/14/16/20, all RGB and YUV 422 8/10 bpc Driver allows to set any format except when RAW10, RAW12 and RAW16 | Added YUV 420 8 bpc support | ||||
| AXI IIC support for Camera Control Interface (CCI) | NA | Removed | |||||
| Filtering based on Virtual Channel Identifier | NA | ||||||
| Support for 1, 2, or 4 pixels per sample at the output | Yes** | ||||||
| AXI4-Lite interface for register access to configure different subsystem options | Yes | ||||||
| Dynamic selection of active lanes within the configured lanes during subsystem generation | Yes | ||||||
| Interrupt generation to indicate subsystem status information | Yes | ||||||
| Internal D-PHY allows direct connection to image sources | Yes | ||||||
| Resource optimization (removed register interface) | NA | No | |||||
*Only RAW8/10/12/16 media bus formats are tested.
**Tested for 1 and 2 pixels per sample
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Known Issues
- AR67896 - MIPI CSI-2 Transmitter Subsystem - Release Notes and Known Issues for the Vivado 2016.3 tool and later versions
Change log
2020.2
- Summary
- Add support for YUV 420 8 bpc
- Fix Coverity warnings
- Commits
2020.1
- Summary
- I2C has been removed and DPHY is now at 4K offset. So IP and driver version has been set to 5.0
- Set source pad format same as sink pad
- Instead of 1, set default number of active lanes as max number of lanes
- Commits
- v4l: xilinx: xcsi2rxss: Move DPHY offset to 4K instead of 64K
- dt-bindings: media: xilinx: csi2rxss: Add 5.0 compatible string
- v4l: xilinx: xcsi2rxss: Add v4.1 compatible string
- dt-bindings: media: xilinx: csi2rxss: Add 4.1 compatible string
- v4l: xilinx: xcsi2rxss: Set default active lanes to max
- v4l: xilinx: xcsi2rxss: Source pad has same format as sink pad
2019.2
- Summary
- Add support to reset IP using external GPIO and stop streaming in case of stream line buffer full condition.
- Commits
- c3e2148 v4l: xilinx: xcsi2rxss: Use external reset in a SLBF condition
2019.1
- Summary
- Add support for common clock framework
- Add support for RAW16 format
- Commits
2018.3
- Summary
- Add support for up to 16 virtual channel VCX when enabled in IP configuration
- Fix to store format size to ensure link_validate passes.
- Commits
2018.2
- Summary
- No changes
2018.1
- Summary
- Add xlnx,mipi-csi2-rx-subsystem-3.0 compatible string
- Fix compilation issue due to framework change
- Commits
2017.4
- Summary
- No changes
2017.3
- Summary
- Fix to handle failure case while creating a custom control
- Commits
- 9921a92 v4l: xilinx: csi2rxss: Handle failing to create custom control
2017.2
- Summary
- Fix a crash caused by update to events counters
- Commit
- e3a7ef8 xcsi2rxss: Fix crash caused by update to event counter variable
2017.1
- Summary
- Fix to support changing the bayer phase at run time
- Commit
- 56e9ba9 xcsi2rxss: Support bayer phase change at run-time
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