This page provides details related to the light weight IP (LWIP) library and the SW app lwip echo server.
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| Family | PHY | Support | Remarks |
|---|---|---|---|
| Zynq | RGMII | Yes | |
| SGMII in PL | Yes | Refer to AR# 66006 | |
| 1000BaseX in PL | Yes | Refer to AR# 66006 | |
| GMII2RGMII convertor in PL | Yes | ||
| ZynqMP | RGMII | Yes | |
| PS SGMII (with fixed link) | Yes | Enable library config parameter "sgmii_fixed_link" (2023.1 and above) | |
| SGMII in PL | Yes | Refer to xapp1306 | |
| 1000BaseX in PL | Yes | Refer to xapp1306 | |
| GMII2RGMII convertor in PL | Yes | ||
| Versal | RGMII | Yes |
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Associating a specific PHY DT node to PS GEM
- Default LWIP PS GEM implementation searches from PHY from address 31 down to 0 to detect a PHY connected over its MDIO.
- In some board configurations, it may be desirable for users to specifically associate a PHY with a given GEM (for example when more than one PHY is connected to the MDIO but GEM0 needs to be used PHY@2). This can be supported by specifying the "phy-handle" devicetree property.
- This devicetree description is already present in the board specific devicetree files for AMD evaluation boards. See versal (applicable to both vmk180 and vck190 boards) for ex., https://github.com/Xilinx/u-boot-xlnx/blob/master/arch/arm/dts/versal-vmk180-revA.dts#L81
- This board devicetree or any customer user defined devicetree snippet can be passed to Vitis Unified IDE while creating a platform, via an Advanced options: https://adaptivesupport.amd.com/s/article/Unlocking-the-Potential-of-the-System-Device-Tree-SDT-in-Vitis-Unified-IDE?language=en_US
2. AXI Ethernet on Microblaze/Zynq/ZynqMP/Microblaze-V
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- No support for 1588
- No Support for 10G/25G
- No MCDMA support
- Performance numbers are not benchmarked on PL interfaces on Microblaze
- lwip perf client application cannot be rerun without a power on reset. For ex., doing rst -proc from xsdb before downloading the executable again does not work. It is required to perform "power 0 power 1" in systest before running a new test.
- AXI Ethernet + FIFO support is not ported to SDT flow
- LWIP examples (IGMP, webserver and TFTP) are not ported to SDT flow.
- Clock change is not automatically handled in lwip adapter for GEM in SDT flow currently. Clock registers can still be manually modified by users. Support for automatically handling this through baremetal clocking framework will be added in an upcoming release.
- LWIP open source code is not supported with C++
- LWIP is not supported with 64 bit Microblaze
- LWIP applications are meant as reference and may not always have board specific support such as specific PHY resets. If there's a GPIO or I2C based reset on board, this can be added to the application by users.
1. GEM
None
2. AXI Ethernet
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https://github.com/Xilinx/embeddedsw/commits/xilinx-v2020.1/ThirdParty/sw_services/lwip211
3e7863e sw_apps: Remove xps_timer reference
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