This page covers the Linux driver for the Xilinx Soft DMA IPs, including AXI DMA, AXI CDMA, AXI MCMDA and AXI VDMA for Zynq, Zynq Ultrascale+ MPSoC, Versal and Microblaze.
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Missing Features and Known Issues/Limitations in Driver
AXI DMA
- No support for Keyhole feature
AXI CDMA
- None
AXI VDMA
- Configurable Burst Size and Line Buffer depth for efficient video streaming
Kernel Configuration
The following config options should be enabled in order to build SoftIP DMA'S(AXI DMA/CDMA/VDMA/MCMDA) driverCONFIG_DMADEVICES
CONFIG_XILINX_DMA
The driver is available at,
https://github.com/Xilinx/linux-xlnx/blob/master/drivers/dma/xilinx/xilinx_dma.c
Devicetree
The device tree node for AXI DMA/CDMA/MCMDA/VDMA will be automatically generated, if the core is configured in the HW design, using the Device Tree BSP.Steps to generate device-tree is documented here,
http://www.wiki.xilinx.com/Build+Device+Tree+Blob
And a sample binding is shown below and the description of DT property is documented here:
AXI DMA
| Code Block | ||
|---|---|---|
| ||
axi_dma_1: dma@40400000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
clocks = <&clkc 15>, <&clkc 15>, <&clkc 15>, <&clkc 15>;
compatible = "xlnx,axi-dma-1.00.a";
interrupt-parent = <&intc>;
interrupts = <0 29 4 0 30 4>;
reg = <0x40400000 0x10000>;
xlnx,addrwidth = <0x20>;
xlnx,include-sg ;
dma-channel@40400000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x1>;
interrupts = <0 29 4>;
xlnx,datawidth = <0x20>;
xlnx,device-id = <0x0>;
xlnx,include-dre ;
};
dma-channel@40400030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
interrupts = <0 30 4>;
xlnx,datawidth = <0x20>;
xlnx,device-id = <0x0>;
xlnx,include-dre ;
};
};
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AXI CDMA
| Code Block | ||
|---|---|---|
| ||
axi_cdma_0: dma@4e200000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_aclk";
clocks = <&&clkc 15>, <&&clkc 15>;
compatible = "xlnx,axi-cdma-1.00.a";
interrupt-parent = <&&intc>;
interrupts = <0 31 4>;
reg = <0x4e200000 0x10000>;
xlnx,addrwidth = <0x20>;
xlnx,include-sg ;
dma-channel@4e200000 {
compatible = "xlnx,axi-cdma-channel";
interrupts = <0 31 4>;
xlnx,datawidth = <0x20>;
xlnx,device-id = <0x0>;
xlnx,include-dre ;
xlnx,max-burst-len = <0x10>;
};
};
|
AXI VDMA
| Code Block | ||
|---|---|---|
| ||
axi_vdma_0: dma@43000000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_s2mm_aclk";
clocks = <&clkc 15>, <&clkc 15>, <&clkc 15>, <&clkc 15>, <&clkc 15>;
compatible = "xlnx,axi-vdma-1.00.a";
interrupt-parent = <&intc>;
interrupts = <0 32 4 0 33 4>;
reg = <0x43000000 0x10000>;
xlnx,addrwidth = <0x20>;
xlnx,flush-fsync = <0x1>;
xlnx,num-fstores = <0x1>;
dma-channel@43000000 {
compatible = "xlnx,axi-vdma-mm2s-channel";
interrupts = <0 32 4>;
xlnx,datawidth = <0x20>;
xlnx,device-id = <0x0>;
xlnx,genlock-mode ;
xlnx,include-dre ;
};
dma-channel@43000030 {
compatible = "xlnx,axi-vdma-s2mm-channel";
interrupts = <0 33 4>;
xlnx,datawidth = <0x20>;
xlnx,device-id = <0x0>;
xlnx,genlock-mode ;
xlnx,include-dre ;
};
};
|
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This test client is available in the Linux source at, https://github.com/Xilinx/linux-xlnx/blob/master/drivers/dma/dmatest.c
For documentation refer to https://www.kernel.org/doc/html/latest/driver-api/dmaengine/dmatest.html
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This test client is available in the Linux source at, https://github.com/Xilinx/linux-xlnx/blob/master/drivers/dma/xilinx/vdmatest.c
The test client can be configured as loadable or in-built kernel module.
Device-tree Node for the test client
Running the test client will display the message when the test is successful,
The test client can be configured as loadable or in-built kernel module.
Device-tree Node for the test client
| Code Block | ||
|---|---|---|
| ||
vdmatest_1: vdmatest@1 {
compatible ="xlnx,axi-vdma-test-1.00.a";
xlnx,num-fstores = <0x3>;
dmas = <&axi_vdma_0 0
&axi_vdma_0 1>;
dma-names = "vdma0", "vdma1";
} ; |
Running the test client will display the message when the test is successful,
| Code Block | ||
|---|---|---|
| ||
vdmatest: Started 1 threads using dma0chan0 dma0chan1 dma0chan0-dma0c: terminating after 1 tests, 0 failures (status 0) |
Mainline Status
The current driver available in the Xilinx Linux git is in sync with the open source kernel driver except for the following- DMA Client driver (axidmatest and vdmatest - these are xilinx specific dma client driver and not streamable)
Change Log
2024.1
- Support for DMA engine based driver to work with a streaming or Ethernet IP drivers.
- Common mainline DT fixes
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- Remove axidma multi-channel mode support
- Fix 64-bit simple AXIDMA transfer
- Fix control reg update in vdma_channel_set_config
Commits:
8c8e3b1 dmaengine: xilinx_dma: Remove axidma multi-channel mode support
c3b6c45 dmaengine: xilinx_dma: Fix 64-bit simple AXIDMA transfer
965442b dmaengine: xilinx_dma: Introduce helper macro for preparing dma address
fbde9af dmaengine: xilinx_dma: Fix control reg update in vdma_channel_set_config
2018.3
- Reset DMA channel in dma_terminate_all.
- Fix 64-bit simple CDMA transfer.
- Code refactoring.
Commits:
1c8b3af dmaengine: xilinx_dma: Reset DMA channel in dma_terminate_all
cf9dfe6 dmaengine: xilinx_dma: Minor refactoring
44b796e dmaengine: xilinx_dma: Fix 64-bit simple CDMA transfer
113e03d dmaengine: xilinx_dma: Move enum xdma_ip_type to driver file
55ea663 dmaengine: xilinx_dma: Fix typos
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