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This page gives an overview of the bare-metal driver support for the Xilinx® LogiCORE™ IP AXI Central Direct Memory Access (CDMA) soft IP.   


Table of Contents

Table of Contents
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The AXI CMDA core is a soft Xilinx IP core for use with the Xilinx Vivado® Design Suite. The AXI CDMA provides high-bandwidth Direct Memory Access (DMA) between a memory-mapped source address and a memory-mapped destination address using the AXI4 protocol. An optional Scatter Gather (SG) feature can be used to offload control and sequencing tasks from the system CPU. Initialization, status, and control registers are accessed through an AXI4-Lite slave interface. For more information, please refer to the AXI CDMA product page which includes links to the official documentation and resource utilization. 

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Test NameExample SourceDescription
Scatter Gather DMA with Interruptsxaxicdma_example_sg_intr.cThis example demonstrates how to transfer packets in interrupt mode when the core is configured in SG Mode.
Scatter Gather DMA with Pollingxaxicdma_example_sg_poll.c This example demonstrates how to transfer packets in the polled mode when the core is configured in SG Mode.
Simple DMA with Interruptxaxicdma_example_simple_intr.c This example demonstrates how to transfer packets in interrupt mode when the core is configured in simple DMA Mode.
Simple DMA with Pollingxaxicdma_example_simple_poll.c  This example demonstrates how to transfer packets in the polled mode when the core is configured in simple DMA Mode.
Hybrid(SG+ simple) with Interruptsxaxicdma_example_hybrid_intr.cThis example demonstrates how to transfer packets in interrupt mode when the core is configured in hybrid(SG + simple) transfer Mode.
Hybrid(SG+ simple) with Pollingxaxicdma_example_hybrid_poll.c

This example demonstrates how to transfer packets in the polled mode when the core is configured in hybrid(SG + simple) transfer Mode.


Example Application Usage

Scatter Gather with Interrupts

This example demonstrates how to transfer packets in interrupt mode when the core is configured in SG Mode.

Expected Output

Code Block
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--- Entering main() ---
Successfully ran XAxiCdma_SgIntr Example
--- Exiting main() ---

Scatter Gather with Polling

This example demonstrates how to transfer packets in the polled mode when the core is configured in SG Mode.

Expected Output

Code Block
themeMidnight
--- Entering main() ---
Successfully ran XAxiCdma_SgPoll Example
--- Exiting main() ---

Simple DMA with Interrupts

This example demonstrates how to transfer packets in interrupt mode when the core is configured in simple DMA Mode.

Expected Output

Code Block
themeMidnight
--- Entering main() ---
Successfully ran XAxiCdma_SimpleIntr Example
--- Exiting main() ---

Simple DMA with Polling

This example demonstrates how to transfer packets in the polled mode when the core is configured in simple DMA Mode.

Expected Output

Code Block
themeMidnight
--- Entering main() ---
Successfully ran AxiCdma_SimplePoll Example
--- Exiting main() ---

Hybrid(SG+ simple) with Interrupts

This example demonstrates how to transfer packets in interrupt mode when the core is configured in hybrid(SG + simple) transfer Mode.

Expected Output

Code Block
themeMidnight
--- Entering main() ---
First simple transfer successful
Scatter gather transfer successful
Second simple transfer successful
Successfully ran Axicdma Hybrid interrupt Example
--- Exiting main() 

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Hybrid(SG+ simple) with Polling

This example demonstrates how to transfer packets in the polled mode when the core is configured in hybrid(SG + simple) transfer Mode.

Expected Output

Code Block
themeMidnight
--- Entering main() ---
First simple transfer successful
Scatter gather transfer successful
Second simple transfer successful
Successfully ran Axicdma Hybrid polled Example
--- Exiting main() 


2023.2

https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2023.2/doc/ChangeLog#L540

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