- zynqmp-clk-ccf.dtsi has static clock node configuration, if user wants to change any of the clock information update those in system-user.dtsi.
- Multi concat Interrupt blocks wont be supported by the DTG.
- DTG doesn't support IP that are packaged in a subsystem(multiple BD's)
- Interrupt port width more than one wont be supported.
- When multicore is enabled for the MAC IPs(if the MAC IPs are more than 1) then there is issue with the label in DTG and it fails. But there wont be an issue if the MAC IP is one and multicore is enabled.
- DTG wont support for generation of private peripheral interrupts(PPI).
- DTG supports the video pipeline generation based on the internal TRD designs as mentioned in the wiki https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/25329832/Zynq+UltraScale+MPSoC+VCU+TRD+2018.3
- DTG doesn't support custom IP, For Multimedia use case If there are any custom IPs connected between the video pipeline IPs DTG wont support those, user may need to add the input and output ports.
- For broadcaster IP the output can connect to multiple output ports and DTG cant know which output port is a valid for the correct pipeline.
- If there are multiple similar video pipelines in the design user need to add the input and output port information in the nodes. The below wiki gives someinfo some info about how to add the input and output ports.
- DTG doesn't support non memory-mapped IP's.
- DTG limitation for multimedia IPs