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This page covers the generation of devicetree source (DTS) files using Xilinx tools as well as the building/compiling of these source files using standard open-source tools.  In particular, use of the Xilinx Devicetree Generator (DTG) will be covered for generating DTS files from a Xilinx hardware project while the devicetree compiler (DTC) will be covered for compiling DTS files into a devicetree binary (DTB).  Although the primary use of the DTB is to provide it to the Linux kernel so that Linux can be initialized to specific hardware correctly, the DTB can also be used with QEMU to emulate hardware for both Linux and standalone systems.

Table of Contents

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  • zynqmp-clk-ccf.dtsi has static clock node configuration, if user wants to change any of the clock information update those in system-user.dtsi.
  • Multi concat Interrupt blocks wont be supported by the DTG.
  • DTG doesn't support IP that are packaged in a subsystem(multiple BD's)
  • Interrupt port width more than one wont be supported.
  • When multicore is enabled for the MAC IPs(if the MAC IPs are more than 1) then there is issue with the label in DTG and it fails. But there wont be an issue if the MAC IP is one and multicore is enabled.
  • DTG wont support for generation of private peripheral interrupts(PPI).
  • DTG supports the video pipeline generation based on the internal TRD designs as mentioned in the wiki https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/25329832/Zynq+UltraScale+MPSoC+VCU+TRD+2018.3
  • DTG doesn't support custom IP, For Multimedia use case If there are any custom IPs connected between the video pipeline IPs DTG wont support those, user may need to add the input and output ports.
  • For broadcaster IP the output can connect to multiple output ports and DTG cant know which output port is a valid for the correct pipeline.
  • If there are multiple similar video pipelines in the design user need to add the input and output port information in the nodes. The below wiki gives someinfo some info about how to add the input and output ports.

New Features for 2020.1:

  • Added mrmac IP initial support.
  • Added DPU IP support
  • Replaced the hardcoded values with the macros for reset and power.
  • Added DTG doesn't support non memory-mapped IP's.
  • With the current DTG implementation not able to populate the ttc timer properties in pcw.dtsi even if the design has ttc ips. In board dtsi file zynq-7000.dtsi/zynqmp.dtsi/versal.dtsi change the ttc timer name to ttctimer then you will see the entries in pcw.dtsi. We will fix this in 2022.2 release.
  • when there are multi ethernet ips in the zynqmp design then getting syntax error for the third IP. Closing the clock with ">" resolves the issue in pl.dtsi file
  • if the same peripheral connected to both RPU and APU and you want only RPU to access that please disable the status explicitly 'status = "disabled"' as DTG default generates the nodes for all the accessible peripherals.

New Features for 2022.1:


List of drivers supported in the DTG and their bindings in Linux tree

  • can, canfd
Bindings from the Linux tree: https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/net/can/xilinx_can.txt
  • axi_cdma
Bindings from the Linux tree: https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/dma/xilinx/axi-cdma.txt
  • axi_dma
Bindings from the Linux tree: https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/dma/xilinx/axi-dma.txt
  • axi_emc
  • axi_ethernet, axi_10g_ethernet,xxv_ethernet
Bindings from the Linux tree: https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/net/xilinx_axienet.txt
  • axi_gpio
Bindings from the Linux tree: https://github.com/Xilinx/linux-xlnx/commits/master/Documentation/devicetree/bindings/gpio/gpio-xilinx.txt
  • axi_iic
Bindings from the Linux tree: https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/i2c/i2c-xiic.txt
  • axi_pcie,axi_pcie3,xdma
Bindings from the Linux tree: https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
  • axi_perf_mon
Bindings from the Linux tree: https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/uio/xilinx_apm.txt
  • axi_quad_spi
Bindings from the Linux tree: https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/spi/spi-xilinx.txt
  • axi_sysace
  • axi_tft
Bindings from the Linux tree: https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/video/xilinx-fb.txt
  • axi_timebase_wdt
Bindings from the Linux tree: https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/watchdog/of-xilinx-wdt.txt
  • axi_traffic_gen
Bindings from the Linux tree: https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/misc/xilinx-axitrafgen.txt
  • axi_usb2_device
Bindings from the Linux tree: https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/usb/udc-xilinx.txt
  • vcu
Bindings from the Linux tree: https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/soc/xilinx/xlnx%2Cvcu.txt
  • axi_vdma
Bindings from the Linux tree: https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
  • xadc_wiz
Bindings from the Linux tree: https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt
  • axi_intc
Bindings from the Linux tree: https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/interrupt-controller/xilinx%2Cintc.txt
  • ddr4,ddr3,mig_7series
  • pr_decoupler
  • usp_rf_data_converter
  • axi_timer
  • tsn_endpoint_ethernet_mac
Bindings from the Linux tree: https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/net/xilinx_tsn.txt
  • axi_uartlite
Bindings from the Linux tree: https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/serial/uartlite.c
  • axi_uart16550
For other IPs DTG will invoke the generic driver.

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Code Block
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make ARCH=arm dtbs

The compiled DTB files will be located in linux-xlnx/arch/arm/boot/dts/.A single /.

A single linux-xlnx/arch/arm/boot/dts/<devicetree name>.dts may be compiled into linux-xlnx/arch/arm/boot/dts/<devicetree name>.dtb:


Code Block
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make ARCH=arm <devicetree name>.dtb


Devicetree Binarys Comparision

Linux source also includes a script for DTB comparisons.  We can check the differences between two devicetree blobs (DTB files) using the dtx_diff binary as below.

Code Block
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cd linux-xlnx/

...

Code Block
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make ARCH=arm <devicetree name>.dtb

Devicetree Binarys Comparision

Linux source also includes a script for DTB comparisons.  We can check the differences between two devicetree blobs (DTB files) using the dtx_diff binary as below.

Code Block
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cd linux-xlnx/scripts/dtc
make ARCH=arm <devicetree name>.dtb
dtx_diff system1.dtb system2.dtb

Advanced DTG Topics

scripts/dtc
make ARCH=arm <devicetree name>.dtb
dtx_diff system1.dtb system2.dtb


Advanced DTG Topics

How to generate dfx supported dtsi files (only for versal)

This section explains how to generate the dtsi files that supports dfx flow.

1.clone the device-tree

https://github.com/Xilinx/device-tree-xlnx.git -b xlnx_rel_v2022.1

2.launch xsct

i.xsct % setws <workspace dir name>

ii.xsct % repo -set <above cloned device-tree-xlnx path>

iii.xsct %  platform create -name dev -hw <static xsa path> -rm-hw <rp-rm xsa path> -proc <proc>  -os device_tree

iv.xsct % bsp config dt_overlay true

v.xsct % platform generate

you will find static and partial dtsi files in the <workspace dir>/dev/psv_cortexa72_0/device_tree_domain/bsp/

convert them into dtbo files using the compiling steps.


How to enable DT OVERLAY from DTG

...

Using HSI commands
1.Clone the device tree repo
https://github.com/Xilinx/device-tree-xlnx
2) Go to the HSI prompt
[vabbarap@xhdl3763 /proj/xhdsswstaff/vabbarap/Overlay/New_hdf> % hsi
hsi v2017.3 (64-bit)SW Build 2018833 on Wed Oct 4 19:58:07 MDT 2017
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
3)
hsi% open_hw_design system.hdf
4)
hsi% set_repo_path /home/vabbarap/workspace/sync_dt_tip/clk_wiz_15_12_2017 (DTG repo path)
5)
hsi% create_sw_design -proc psu_cortexa53_0 sd22 -os device_tree
6)
hsi% set_property CONFIG.dt_overlay true [get_os]
7)
hsi% generate_target -dir dt/
hsi% ls dt/
pcw.dtsi pl.dtsi sd22.mss system-top.dts zynqmp-clk-ccf.dtsi zynqmp.dtsi

Using XSCT (From 2019.2 release no hsi support)

...

3) hsi open_hw_design system.xsa

4) hsi set_repo_path /home/vabbarap/workspace/sync_dt_tip/dt_15_12_2019 (DTG repo path)

5) hsi create_sw_design -proc psu_cortexa53_0 sd22 -os device_tree 

...

Release Notes

Build Steps

Related Links