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Table of Contents

Table of Contents


This page gives an overview of standalone BSP which is available as part of the Xilinx Vivado and Vitis distribution.

Table of Contents

Table of Contents


Xilinx provides support for Microblaze, Cortex-A9, Cortex-R5, Cortex-A53 and Cortex-A72 processors that does bringup and provides interface for processor related functionalities like caches.

Standalone BSP Sources

The source code for the BSP is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository. 

Component Name

Path in Vitis

Path in Github


<Vitis Install Directory>/data/embedded/lib/bsp/standalone


Note: To view the sources for a particular release, use the rel-version tag in github.  For example, for the 2020.1 release, the proper version of the code is:

The driver source code is organized into different folders.  The table below shows the standalone BSP source organization. 



Provides the API and data structure details


Driver .tcl and .mld file


Example applications that show how to use the BSP features


Driver source files


Xilinx provides support for Microblaze, Cortex-A9, Cortex-R5, Cortex-A53 and Cortex-A72 processors.
The standalone BSP performs the processor bring up and provides interface to the user to carry out processor related functionalities naming a few Interrupt enable/disable, device configuration, cache access etc.

To build the BSP, default toolchains are configured with the help of CPU driver. The CPU drivers configure toolchain, archiver and extra compiler flag related settings for a particular bsp. The BSP and drivers are compiled with the same settings. The code for cpu driver can be found at:
cpu_cortexa53 (for Cortex-A53)
cpu_cortexa72 (for Cortex-A72)
cpu_cortexa9 (for Cortex-A9)
cpu_cortexr5 (for Cortex-R5)
cpu (for Microblaze)

The application is built on top of standalone BSP and drivers. The application starts with boot code, doing the processor initialization, soc configuration if required any, toolchain related functionalities if required and reaching to application main. The BSP provide simplified interface to access processor and soc related functionalities.

Features Supported:

ARM Processors (Cortex-A9, Cortex-R5, Cortex-A53, Cortex-A72):

Common Features in ARM BSP:

  • Boot code
  • Cache Flush/Invalidation
  • Interrupt/Exception handling
  • Lite printf version (xil_printf)
  • Memory/IO access through APIs
  • Sleep functionality with busy loop
  • C interface for frequently used assembly instructions
  • Endianness: Little endian

Cortex-A9 BSP supported features:

  • Device/Memory attribute configuration in MMU as per requirement (Default configuration is done by Boot code)
  • Floating point support
  • Nested interrupt support
  • Snoop control unit
  • Global timer access
  • Execution at System Mode
  • Different compiler support:
    • gcc
    • armcc
    • iar

Cortex-R5 BSP supported features:

  • Device/Memory attribute configuration in MPU as per requirement (Default configuration is done by Boot code)
  • Vectors in TCM for low latency interrupt
  • Nested interrupt support
  • Execution at System Mode
  • gcc and IAR compiler support

ARMv8 BSP supported features:

  • AArch64 and AArch32 mode
  • Support for Cortex-A53 and Cortex-A72 processors
  • Execution at Secure Monitor Level EL3 for AArch64 and System mode for AArch32
  • AArch64 BSP supports EL1 Non-secure execution on hypervisor
  • Device/Memory attribute configuration in MMU as per requirement (Default configuration is done by Boot code)
  • Generic counter accessibility
  • gcc compiler support
  • Floating point support
  • Xen PV console support for Cortex A53 EL1 NS domU guests

Boot Sequence for ARM Processors:

When application software needs to be executed on processor, there are certain configuration needs to be done which are done as part of boot code. When an application is built with Xilinx standalone bsp, following is a sequence illustrating how an application starts and reaches to main function.
  • Program vector table base for exception handling
  • Invalidate cache, TLBs
  • Program stack pointer for various modes
  • Configure MMU/MPU
  • Enable data cache, instruction cache and MMU/MPU
  • Clearing of BSS sections
  • Running global constructor
  • Jumping to application main

MMU/MPU Configuration for ARM Processors

  • MMU configuration:
    • The translation table is a flat mapped (input address is same as output address) static translation table. The size of the pages in translation table is decided based on the processor architecture and platform requirement. The attribute of the particular page in a translation table are defined as per the default address map, and they can be changed as per user need during main application by using an API provided by BSP.
  • MPU Configuration:
    • There are limited number of regions which can be configured to denote the attributes in MPU. Some of the regions are configured by default at the time of booting of the processor as per architecture and platform requirement. The remaining regions can be utilized by user in the application main to configure as per their requirement using BSP API.

Known issues and Limitations

  • Cortex-a53 AArch64 EL1 NS execution : Xen PV console for standalone domU supports only stdout functions, stdin function (i.e. scanf) is not supported

Example Applications

Refer to the BSP examples directory for various example applications that exercise the different features of the BSP. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. 

Links to Examples

Examples Path:

Test Name

Example Source

Nested interrupt example


Implements example that demonstrates usage of macros available for nested
interrupt handling in xil_exception.h
Cortex-R5 PMU counter example


Implements example that demonstrates usage of R5 PMU counters and the
available APIs provided through xpm_counter.c.

Example Application Usage

Nested interrupt example