Table of Contents
|Table of Contents|
The AXI VDMA core is a soft Xilinx IP core for use with the Xilinx Vivado® Design Suite. It provides high-bandwidth direct Memory access between memory and AXI4-Stream video type target peripherals including peripherals which support the AXI4-Stream Video protocol as described in the Video IP:AXI Feature Adoption section of the Vivado AXI Reference Guide (UG1037)
For more information, please refer to the AXI VDMA product page which includes links to the official documentation and resource utilization.
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
<If there are multiple drivers supporting this IP, we should make that statement here and add to the table>
|Driver Name||Path in Vitis||Path in Github|
|axivdma||<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/axivdma_<version>||https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/axivdma|
Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/axivdma
The driver source code is organized into different folders. The table below shows the axivdma driver source organization.
Provides the API and data structure details
|data||Driver .tcl and .mdd file|
|examples||Example applications that show how to use the driver features|
|src||Driver source files|
For a full list of features supported by this IP, please refer to the AXI VDMA product page.
FeaturesThe AXI VDMA Standalone driver supports the following features:
- Supports 64-bit Addressing
- Supports Gen-Lock Synchronization
- Supports up to 32 frame buffers
- Supports frame advance or repeat on error
- Supports Parking Mode
- Supports Circular Buffer Mode
Known Issues and Limitations
The following is a list of known limitations of the driver and features of the IP that are not currently implemented:
- When H/w is configured without DRE driver will throw an error if the user sends an unaligned buffer address.
- User application should handle buffer address alignment in case h/w is configured without DRE
Example Design Architecture
The examples assumes AXI VDMA IP is configured in loopback mode.
Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.
Links to Examples
|Test Name||Example Source||Description|
|Self Test||xaxivdma_example_selftest.c||This example does a basic reset of the core and checks core is coming out of reset or not.|
|Video Frame transfer with interrupts||xaxivdma_example_intr.c||This example demonstrates how to do video frame transfers in AXI Video DMA loopback mode. This example reads video frames from memory, using Memory Map to Stream (MM2S) interface, and then video frames are written to memory using Stream to Memory Map (S2MM) AXI4 interface. At the end of transfer it does sanity check and report pass/fail status.|
Example Application Usage
This example does a basic reset of the core and checks core is coming out of reset or not.
--- Entering main() --- Successfully ran AxiVDMASelfTest Example --- Exiting main() ---
Video Frame transfer with interrupts
This example demonstrates how to do video frame transfers in AXI Video DMA loopback mode.
--- Entering main() --- Successfully ran axivdma intr Example --- Exiting main() ---