| Table of Contents |
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Introduction
This page gives an overview of uartps driver which is available as part of the Xilinx Vivado and SDK distribution....
Driver Sources
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
| Driver Name | Path in Vitis | Path in Github |
|---|---|---|
| uartps | <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/uartps | https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/uartps |
| Info |
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Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/uartps |
The driver source code is organized into different folders. The table below shows the uartps driver source organization.
Directory | Description |
|---|---|
doc | Provides the API and data structure details |
data | Driver .tcl and .mdd file |
examples | Example applications that show how to use the driver features |
| src | Driver source files |
Driver Implementation
For a full list of features supported by this IP, please refer zynqmp TRM which includes link s to the official documentation and resource utilization.
Features
Programmable baud rate generator64-byte receive and transmit FIFOs
Programmable protocol:
6, 7, or 8 data bits
1, 1.5, or 2 stop bits
Odd, even, space, mark, or no parity
Parity, framing and overrun error detection
Line-break generation and detection
Interrupts generation
RxD and TxD modes: Normal/echo and diagnostic loopbacks using the mode switch
The following features are supported in the uartps Standalone driver.
Loop UART 0 with UART 1 option
Modem control signals: CTS, RTS, DSR, DTR, RI and DCD are available only on the EMIO interface
...
| Code Block |
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HelloWorld Successfully ran Uartps hello world Example |
Example Design Architecture
NA
Change Log
2021.2
None
2021.1
...