Versions Compared

Old Version 11

changes.mady.by.user Raviteja Narayanam

Saved on

compared with

New Version 12

changes.mady.by.user Raviteja Narayanam

Saved on

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

Table of Contents


Introduction

This page gives an overview of uartps driver which is available as part of the Xilinx Vivado and SDK distribution.

Source path for the driver:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/uartps

Driver source code is organized into different folders. Below diagram shows the uartps driver source organization
uartps
|
-- Doc - Provides the API and data structure details
|
- Examples - Reference application to show how to use the driver APIs and calling sequence
|
- Source - Driver source files

.

Controller Features Supported:

Programmable baud rate generator
64-byte receive and transmit FIFOs
Programmable protocol:
6, 7, or 8 data bits
1, 1.5, or 2 stop bits
Odd, even, space, mark, or no parity
Parity, framing and overrun error detection
Line-break generation and detection
Interrupts generation
RxD and TxD modes: Normal/echo and diagnostic loopbacks using the mode switch

The following features are supported in the uartps Standalone driver.
Loop UART 0 with UART 1 option
Modem control signals: CTS, RTS, DSR, DTR, RI and DCD are available only on the EMIO interface

Standalone Driver Supported Features

The uartps Standalone driver support the below things.
Programmable baud rate generator
64-byte receive and transmit FIFOs
Parity, framing and overrun error detection
Line-break generation and detection
Interrupts generation
RxD and TxD modes: Normal/echo and diagnostic loopbacks using the mode switch

Known issues and Limitations
  • None

Test cases

Refer below pah for testing different examples for each feature of the IP.
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/uartps/examples

ChangeLog

2016.3
Summary:
  • uartps: Modified the transmission break bit set logic.
Commits:
  • e4285c4 uartps: Modified the transmission break bit set logic.

2016.4
  • None

2017.1
Summary:
  • xuartps: Fixed compilation warnings
  • uartps: sync UART_CLK_FREQ_HZ parameter with xparameters.h file uart frequency parameter macro
  • uartps : Fixed compilation warnings
  • uartps : Added xil_printf statement in examples
  • uartps: Added readme.txt file to generate doxygen for examples
Commits:
  • 64da84b xuartps : Fixed compilation warnings
  • 74c9d16 uartps: sync UART_CLK_FREQ_HZ parameter with xparameters.h file uart frequency parameter macro
  • 9f97f45 uartps: Fixed compilation warnings
  • e11fddf uartps : Added xil_printf statement in examples
  • d586063 uartps: Added readme.txt file to generate doxygen for examples

2017.2
  • None

2017.3
Summary:
  • Updated the source files to updated addtogroup version numbers
Commits:
  • 04cf58b Updated the source files to updated addtogroup version numbers

2017.4
Summary:
  • xuartps: Fix the Buffer Overflow issue in the Receive path.
Commits:
  • ebf447c xuartps: Fix the Buffer Overflow issue in the Receive path.

2018.1

  • None

2018.2

  • None

2018.3

Summary:

  • uartps: Resolves MISRA-C:2012 compliance mandatory violations.

Commits:

  • 04cf58b uartps: Resolves MISRA-C:2012 compliance mandatory violations.

2019.1

  • None

2019.2

  • None

2020.1

2020.2