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The purpose of this page is to discuss the hardware and software requirements needed to allow PL Masters to operate within a Xen Hypervisor system configuration.
Table of Contents
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1 Introduction
The Programmable Logic (PL) of the FPGA provides the flexibility to move data using AXI Masters such as DMA or custom IP. When Xen is running on ZynqMP the SMMU is used control data movement from the PL to any guest domains. This page describes the details needed to make an AXI Master in the PL work with a guest running in Xen. There is a focus on bare metal guests running on Xen with testing based on the 2017.1 release.
This information is based on early prototyping such that there are still some remaining questions and changes are likely. This page also assumes the user understands Xen and the process of passing through a device to a guest domain.
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The SMMU implements a TBU for sets of masters based on the PS port. Refer to the Zynq MPSOC TRM for more TBU details. The following table specifies the TBU number associated with each port of the Zynq MPSOC PS.
| TBU Number | PS Port |
| 0 | S_AXI_HPC[0]_FPD |
| 0 | S_AXI_HPC[1]_FPD |
| 3 | S_AXI_HP[0]_FPD |
| 4 | S_AXI_HP[1]_FPD |
| 4 | S_AXI_HP[2]_FPD |
| 5 | S_AXI_HP[3]_FPD |
3 Stream IDs
Many of the complexities of a PL Master revolve around stream IDs. The details are explained in the following sub-paragraphs.
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