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This page gives an overview of nandpsu driver which is available as part of the Xilinx Vivado and SDK distribution.
Source path for the driver:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/nandpsu
Driver source code is organized into different folders. Below diagram shows the nandpsu driver source organization
nandpsu
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-- Doc - Provides the API and data structure details
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- Examples - Reference application to show how to use the driver APIs and calling sequence
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- Source - Driver source files
Source path for the driver:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/nandpsu
Driver source code is organized into different folders. Below diagram shows the nandpsu driver source organization
nandpsu
|
-- Doc - Provides the API and data structure details
|
- Examples - Reference application to show how to use the driver APIs and calling sequence
|
- Source - Driver source files
Features Supported
Controller Features:
- Complies with the ONFI 3.1 specification
- Supports interleaving operations
- Supports BCH error correction code (ECC) data widths of 4, 8, 12, and 24 bits.
- All ONFI 3.1 commands
- PIO and MDMA support
- SDR and NVDDR modes
- supports only 8-bit bus support
- Hardware ECC (Hamming code and BCH)
- Page size up to 16K
- Programmable timing modes
- 64-bit dma support.
- Supports multiple chip selects (up to 2)
Driver Features:
- Supports only the mandatory ONFI 3.1 commands. i.e Reset, Read status, Read ID, Read Parameter Page, Read Page, Program Page, Erase Block, Set/Get Features
- Supports SDR/DDR modes
- Supports timing modes 0-5
- Supports PIO and MDMA support
- Support for multiple chip selection
- Support BBT management
Bad Block management
Bad block management implementation is same as Linux MTD bad block management with the exception of reserving number of blocks to store Bad Block Table (BBT) from default 4 blocks to 64 blocks. This is because one of the Micron flash part MT29F32G08ABCDB has last 32 blocks as bad most of the times. Since it was difficult to store bad block table in last 4 blocks, the number of blocks are increased to 64 blocks.Known issues and Limitations
- Driver supports polled mode only
- No support for interleaved and all optional ONFI 3.1 commands
ChangeLog
2016.3
- Summary
- None
- Commits
- None
- Summary
2016.4
- Summary
- None
- Commits
- None
- Summary
2017.1
- Summary
- Fix for reading nand redundant parameter pages
- Commit id
- Summary
2017.2
- Summary
- None
- Commits
- None
- Summary
2017.3
- Summary
- Added CCI support
- Commit
- Summary
2017.4
- Summary
- None
- Commits
- None
- Summary
2018.1
- Summary
- None
- Commits
- None
- Summary
2018.2
- Summary
- None
- Commits
- None
- Summary
2018.3
- Summary
- Support 64 bit DMA addresses for Microblaze-X
- Commit
- Summary
2019.1
- Summary
- None
- Commits
- None
- Summary
2019.2
- Summary
- None
- Commits
- None
- Summary
2020.1
- Added clock supportSummary
- Add clocking support
- Commits
- Added clock supportSummary
2020.2
- Summary
- None
- Commits
- None
- Summary
Test cases
Nandpsu example:
https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/nandpsu/examples/xnandpsu_example.cIt verifies the nand data integrity by programing the known data pattern and verify the same by reading the data back.
In this process erase, program, read, read ID, Read Parameter Page, Reset, read status, get/set features and bbt management are covered
Output:
| Code Block | ||
|---|---|---|
| ||
Xilinx Zynq MP First Stage Boot Loader Release 2020.1 May 24 2020 - 13:51:37 Nand Flash Read Write Example Test Manufacturer: MICRON MT29F32G08ABCDBJ4 , Device Model: MT29F32G08ABCDBJ4 , Jedec ID: 0x2C Bytes Per Page: 0x4000 Spare Bytes Per Page: 0x4C0 Pages Per Block: 0x100 Blocks Per LUN: 0x418 Number of LUNs: 0x1 Number of bits per cell: 0x1 Number of ECC bits: 0xFF Block Size: 0x400000 Number of Target Blocks: 0x418 Number of Target Pages: 0x41800 ECC: addr 0x4220 size 0x2A0 numbits 24 codesz 10 XNandPsu_ReadBbt: Bad block table found Successfully ran Nand Flash Read Write Example Test |
Performance:
| Timing Mode | Write(MBPS) | Read(MBPS) |
| SDR mode 0 | 6.4 | 7.7 |
| SDR mode 1 | 11.2 | 15.1 |
| SDR mode 2 | 13.0 | 18.7 |
| SDR mode 3 | 15.1 | 24.4 |
| SDR mode 4 | 15.6 | 24.5 |
| SDR mode 5 | 15.7 | 24.5 |
| NVDDR mode 0 | 31.0 | 107.7 |
| NVDDR mode 1 | 31.0 | 106.2 |
| NVDDR mode 2 | 31.0 | 106.3 |
| NVDDR mode 3 | 31.0 | 107 |
| NVDDR mode 4 | 31.0 | 106.3 |
| NVDDR mode 5 | 31.0 | 106.3 |