Introduction
This page provides details related to the standalone emacps driver. This driver supports GEM on Zynq, Zynq Ultrascale+ MPSoC and Versal. For more information, please refer to GEM Ethernet chapter in Zynq TRM (UG585), ZynqMP TRM (UG1085) or Versal TRM (AM011).
Driver Sources
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
Driver Name | Path in Vitis | Path in Github |
---|---|---|
emapcs | <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/emacps | https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/emacps |
Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx_v2021.1/XilinxProcessorIPLib/drivers/emacps |
The driver source code is organized into different folders. The table below shows the emacps driver source organization.
Directory | Description |
---|---|
doc | Provides the API and data structure details |
data | Driver .tcl, .mdd file and .yaml files |
examples | Example applications that show how to use the driver features |
src | Driver source files, make and cmake files |
Note: AMD Xilinx embeddedsw build flow is changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki page Porting embeddedsw components to system device tree (SDT) based flow - Xilinx Wiki - Confluence (atlassian.net).
The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in the future.
Driver Implementation
For a full list of features supported by this IP, please refer to GEM Chapter in Zynq TRM (UG585), ZynqMP TRM (UG1085) or Versal TRM (AM011) for respective devices.
Features
Controller/Driver features supported
10/100/1000 speeds, phy/external loop back (supported in emacps
PHY management
DMA, Packet buffer support, Checksum offload, FCS stripping, programmable IPG, multicasting, promiscuous and broadcast modes.
Flow control and half duplex features are supported by controller but not demonstrated in the examples.
ZynqMP and Versal only: 64 bit descriptor support, Priority queue support, Jumbo frame support, CCI support
PHY configurations
emacps driver supports the following PHY configurations:
Family | PHY | Support |
---|---|---|
Zynq | RGMII | Yes - supported in HW and driver |
ZynqMP | RGMII | Yes - supported in HW and driver |
ZynqMP | SGMII | Yes - supported in HW and driver |
Versal | RGMII | Yes - supported in HW and driver |
Known Issues and Limitations
The following features are not supported:
External FIFO interface - this driver only targets DMA
Partial store and forward not supported
- Clock change is not automatically handled in the example in SDT flow currently. Clock registers can still be manually modified by users. Support for automatically handling this through baremetal clocking framework will be added in an upcoming release.
Interop
PHY device Marvell 88E1116 has been tested on Zynq evaluation board
PHY devices Marvell 88E1512, TI DP83867 (RGMII and SGMII), VSC8211 and RTL8211 have been tested on ZynqMP.
PHY devices Marvell 88E1512, TI DP83867, VSC8531_02 and RTL8211DN have been tested on Versal.
Example Applications
Emacps driver supports a DMA based loopback example and it describes how its different features can be exercised. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.
Links to Examples
Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/emacps
Test Name | Example Source | Description |
---|---|---|
Emacps DMA loopback example | Emacps basic DMA loopback examples sends and receives a single frame in loopback mode. |
Note: emacps 1588 examples were deprecated as they were originally added as a reference for Zynq-7000 but the timestamping logic in that version of the IP has issues, rendering this feature unusable. These examples were removed in 2021.1 release.
Example Application Usage
Emacps DMA loopback example
Emacps basic DMA loopback examples sends and receives a single frame in loopback mode.
Expected Output
Code Block | ||
---|---|---|
| ||
Entering into main() Success in examples |
Example Design Architecture
NA
Performance
Standalone ethernet performance is benchmarked with the use of light weight IP library and application. Please refer to
http://www.wiki.xilinx.com/Standalone+LWIP+library#Performance
Change Log
2024.1
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2024.1/doc/ChangeLog#L407
2023.2
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2023.2/doc/ChangeLog#L197
2023.1
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2023.1/doc/ChangeLog#L87
2022.2
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2022.2/doc/ChangeLog#L96
2022.1
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2022.1/doc/ChangeLog#L27
2021.2
https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2021.2/doc/ChangeLog#L62
2021.1
https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2021.1/doc/ChangeLog#L426
2020.2
https://github.com/Xilinx/embeddedsw/blob/release-2020.2/doc/ChangeLog#L450
2020.1
https://github.com/Xilinx/embeddedsw/blob/release-2020.1/doc/ChangeLog#L36
2019.2
https://github.com/Xilinx/embeddedsw/blob/release-2019.2/doc/ChangeLog#L36
2019.1
https://github.com/Xilinx/embeddedsw/blob/release-2019.1/doc/ChangeLog#L75
2018.3
https://github.com/Xilinx/embeddedsw/blob/release-2018.3/doc/ChangeLog#L126
2018.2
None
2018.1
https://github.com/Xilinx/embeddedsw/blob/release-2018.1/doc/ChangeLog#L131
2017.4
https://github.com/Xilinx/embeddedsw/blob/release-2017.4/doc/ChangeLog#L21
2017.3
https://github.com/Xilinx/embeddedsw/blob/release-2017.3/doc/ChangeLog#L368
Related Links
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