Known Issues and Limitations

• https://www.xilinx.com/support/answers/68246.html

• https://www.xilinx.com/support/answers/69125.html

Example Applications

Refer to the driver examples directory for various example applications that exercise the different features of the driver.

Each application is linked in the table below. The following sections describe the usage and expected output of the various applications.

These example applications can be imported into the Vitis IDE from the Board Support Package settings tab. 

Links to Examples

Examples Path: https://github.com/Xilinx/embeddedsw/tree/master/lib/sw_services/xilfpga/examples

Example Application Usage

Full Bitstream/PDI loading

Transfer the user provided Full Reconfiguration Bitstream into the PL.

Expected Output

Loading Bitstream for DDR location :0x80000
Trying to configure the PL ......
PL Configuration done successfully

Partial Bitstream/PDI loading

Transfer the user provided Partial Reconfiguration Bitstream into the PL Region.

Expected Output

Loading Partial Reconfiguration Bitstream from DDR location :0x80000
Trying to configure Partial Reconfiguration Bitstream into the PL ......
Partial Reconfiguration Bitstream loaded into the PL successfully

Readback of configuration registers

This example prints out the values of all the configuration registers related to FPGA

Expected Output

Register Read back example
Value of the Configuration Registers.
CRC ->   0 
FAR ->   7fc0000   
FDRI ->      0 
FDRO ->      effffffe  
CMD ->   d 
CTRL0 ->     101   
MASK ->      0 
STAT ->      16907ffc  
LOUT ->      0 
COR0 ->      38003fe5  
MFWR ->      0 
CBC ->   0 
IDCODE ->    1484a093  
AXSS ->      0 
COR1 ->      400000    
WBSTR ->     0 
TIMER ->     0 
BOOTSTS ->   1 
CTRL1 ->     0
Successfully ran Register Read back example

Readback of configuration Data

This example prints out the fpga configuration data.

Expected Output

FPGA Configuration data Read back example
0000 00000 00000 0000 0000
.... ..... ..... .... ....
.... ..... ..... .... ....
.... ..... .... .... ....
Successfully ran FPGA Configuration Read back example

ChangeLog

• 2024.1
  • https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2024.1/doc/ChangeLog#L976
• 2023.2
  • https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2023.2/doc/ChangeLog#L338

• 2023.1
  • https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2023.1/doc/ChangeLog#L168
• 2022.1
  • https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2022.2/doc/ChangeLog#L1109
• 2022.1
  • https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2022.1/doc/ChangeLog#L136
• 2021.2
  • https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2021.2/doc/ChangeLog#L75
• 2021.1
  • https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L332 
• 2020.2
  • https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.2/doc/ChangeLog#L724
• 2020.1
  • https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.1/doc/ChangeLog#L170
• 2019.2
  • https://github.com/Xilinx/embeddedsw/blob/xilinx-v2019.2/doc/ChangeLog#L434
• 2019.1
  • https://github.com/Xilinx/embeddedsw/blob/xilinx-v2019.1/doc/ChangeLog#L193
• 2018.3
  • https://github.com/Xilinx/embeddedsw/blob/xilinx-v2018.3/doc/ChangeLog#L315
• 2018.2
  • https://github.com/Xilinx/embeddedsw/blob/xilinx-v2018.2/doc/ChangeLog#L104
• 2018.1
  • https://github.com/Xilinx/embeddedsw/blob/xilinx-v2018.1/doc/ChangeLog#L341
• 2017.4
  • https://github.com/Xilinx/embeddedsw/blob/xilinx-v2017.4/doc/ChangeLog#L383
• 2017.3
  • https://github.com/Xilinx/embeddedsw/blob/xilinx-v2017.3/doc/ChangeLog#L325
• 2017.2
  • https://github.com/Xilinx/embeddedsw/blob/xilinx-v2017.2/doc/ChangeLog#L34
• 2017.1
  • https://github.com/Xilinx/embeddedsw/blob/xilinx-v2017.1/doc/ChangeLog#L435
• 2016.4
  • https://github.com/Xilinx/embeddedsw/blob/xilinx-v2016.4/doc/ChangeLog#L13
• 2016.3
  • https://github.com/Xilinx/embeddedsw/blob/xilinx-v2016.3/doc/ChangeLog#L437

Related Links

• http://www.wiki.xilinx.com/Baremetal+Drivers+and+Libraries