Introduction‍

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The Xilinx device tree generator (https://github.com/Xilinx/device-tree-xlnx) currently lacks automated support for device tree overlay generation for Partial Reconfiguration / DFX designs.  For systems requiring runtime device tree overlay (eg, Linux device driver support) support, hand-crafted device trees can be deployed and loaded. See the "Working with Device Tree Overlay (DTBO)" section below for details on how to load these at runtime.

Occasionally, bare-metal applications relying on the XilFPGA library may produce an error getting the DONE status.  See Answer Record 70504 for more details - https://www.xilinx.com/support/answers/70504.html 

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      4. Use petalinux-build command to build the required images

# petalinux-build 

Once build is complete, binaries are available at images/linux directory            

      5. Boot the hardware with newly built images

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# bitbake core-image-minimal 

Once build is complete, binaries are available at images/linux directory            

      3. Boot the hardware with newly built images

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•   Linux FPGA Manager framework provides sysfs (Bitstream loading), debugfs (readback), configfs (Bitstream loading along with DTBO for PL drivers) attributes.
•   Alternatively users can opt for Xilinx developed fpgautil. This utility provides an easy to use interface for programmers for all FPGA Manager use cases.    See Note 2 above with respect to partial bitstreams.

Exercising FPGA programming using fpgautil 

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root@xilinx-zcu102-2018_3:~# fpgautil  -b /mnt/design_1_wrapper.bit
Time taken to load BIN is 213.000000 Milli Seconds
BIN FILE loaded through zynqMP FPGA manager successfully

Loading Partial Bitstream that doesn't require PL drivers

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Usage: fpgautil -b <bit/bin file full path> -f Partial 

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Code Block
theme Midnight
root@xilinx-zcu102-2018_3:~# fpgautil -r readbackdata -t 1 root@xilinx-zcu102-2018_3:~# hexdump readbackdata.bin > data.txt

Verification of Read-back Data

• To verify the readback data stream, compare it to the RBD golden readback file and masking readback bits with the MSD file. This approach is simple because there is a 1:1 correspondence between the start of the readback data stream and the start of the RBD and MSD files, making the task of aligning readback, mask, and expected data easier.

• The RBD and MSD files contain an ASCII representation of the readback and mask data along with a file header that lists the file name, etc. This header information should be ignored or deleted. The ASCII 1s and 0s in the RBD and MSD files correspond to the binary readback data from the device.

• For generating RBD and MSD refer UG908 (Vivado Design Suite User Guide)

  By compiling the below utility(verify_readback.c file) user can verify the read back contents.
  Source code: verify_readback

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• firmware:  /sys/class/fpga_manager/<fpga>/firmware
  firmware attribute requests an fpga image using the firmware class, then write output to the FPGA
• flags:  /sys/class/fpga_manager/<fpga>/flags
  flags attribute determines the type of Bitstream 
  0 - Full Bitstream 1 - Partial Bitstream (default: 0, See Note 2 above)
• state:  /sys/class/fpga_manager/<fpga>/state
  state attribute is a superset of FPGA states and FPGA Manager driver states
• name:  /sys/class/fpga_manager/<fpga>/name
  name attribute is name of the low level FPGA Manager driver 
• key: /sys/class/fpga_manager/<fpga>/key 
  key attribute stores the key value useful for Encrypted Bitstream loading to read the userkey
   

Steps for programming the Full Bitstream 

Set flags for Full Bitstream

• echo 0 > /sys/class/fpga_manager/fpga0/flags

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• mkdir -p /lib/firmware

• cp /media/design_1_wrapper.bit.bin /lib/firmware/

• echo design_1_wrapper.bit.bin > /sys/class/fpga_manager/fpga0/firmware

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Steps for Readback of Configuration Registers

Set flags for readback type

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Steps for Readback of Configuration DataFrames 

Set flags for readback type

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//Device Tree Example: Full Reconfiguration along with PS PL Configuration (Clock, resets and AFI)
// HSI Generated overlay/pl.dtsi file.
// Enable the axi-gpio interface
/dts-v1/;
/plugin/;
/ {
	fragment@0 { /* Bitstream  Fragment */ 
		target = <&fpga_full>;
		overlay0: __overlay__ {
			#address-cells = <2>;
			#size-cells = <2>;
			firmware-name = "design_1_wrapper.bit.bin";
			resets = <&rst 116>;
		};
	};
	fragment@1 { /* PS-PL configuration Fragment */
		target = <&amba>;
		overlay1: __overlay__ {
			afi0: afi0 {
				compatible = "xlnx,afi-fpga";
				config-afi = < 0 0>, <1 0>, <2 0>, <3 0>, <4 0>, <5 0>, <6 0>, <7 0>, <8 0>, <9 0>, <10 0>, <11 0>, <12 0>, <13 0>, <14 0>, <14 0>, <15 0x000>;
			};
			clocking0: clocking0 {
				#clock-cells = <0>;
				assigned-clock-rates = <99990005>;
				assigned-clocks = <&clk 71>;
				clock-output-names = "fabric_clk";
				clocks = <&clk 71>;
				compatible = "xlnx,fclk";
			};
		};
	};
	fragment@2 { /* PL Drivers Fragment */
		target = <&amba>;
		overlay2: __overlay__ {
			axi_gpio_0: gpio@a0000000 {
				#gpio-cells = <3>;
				#interrupt-cells = <2>;
				clock-names = "s_axi_aclk";
				clocks = <&clk 71>;
				compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a";
				gpio-controller ;
				interrupt-controller ;
				interrupt-names = "ip2intc_irpt";
				interrupt-parent = <&gic>;
				interrupts = <0 89 4>;
				reg = <0x0 0xa0000000 0x0 0x1000>;
				xlnx,all-inputs = <0x1>;
				xlnx,all-inputs-2 = <0x0>;
				xlnx,all-outputs = <0x0>;
				xlnx,all-outputs-2 = <0x1>;
				xlnx,dout-default = <0x00000000>;
				xlnx,dout-default-2 = <0xAAAAAAAA>;
				xlnx,gpio-width = <0x8>;
				xlnx,gpio2-width = <0x8>;
				xlnx,interrupt-present = <0x1>;
				xlnx,is-dual = <0x1>;
				xlnx,tri-default = <0xFFFFFFFF>;
				xlnx,tri-default-2 = <0xFFFFFFFF>;
			};
			psu_ctrl_ipi: PERIPHERAL@ff380000 {
				/* This is a place holder node for a custom IP, user may need to update the entries */
				compatible = "xlnx,PERIPHERAL-1.0";
				reg = <0x0 0xff380000 0x0 0x80000>;
			};
			psu_message_buffers: PERIPHERAL@ff990000 {
				/* This is a place holder node for a custom IP, user may need to update the entries */
				compatible = "xlnx,PERIPHERAL-1.0";
				reg = <0x0 0xff990000 0x0 0x10000>;
			};
		};
	};
};

Working with Device Tree Overlay (DTBO)

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There is no out-of-box tool flow support for loading Partial Bitstreams that need PL drivers. The creation of DTO files needed for this approach is not supported in the tool flow (DTG, Petalinux, Yocto).

Users can still achieve their goal of programming partial bitstreams that need PL driver support by using hand-written DTSi files.

Steps for programming the Partial Bitstream using handwritten dtsi file

Copy the Partial Bitstream (.Copy the Partial Bitstream (.bin) and rm.dtbo files into lib/firmware folder

• mkdir /configfs

• mount -t configfs configfs /configfs

• cd /configfs/device-tree/overlays/

• mkdir partial

• echo 1 > /sys/class/fpga_manager/fpga0/flags

• echo -n "pl.dtbo" > partial/path

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To remove a device tree overlay:

• rmdir /configfs/device-tree/overlays/partial

Mainline Status

The current driver availble in the xilinx linux git is in sync with the open source 4.19 kernel driver except for the following

• Encrypted and Authenticated Full/Partial Bitstream loading
• Readback of Configuration Registers
• Readback of Bitstream(Configuration Data)

Release history

2020.2

Summary:

• fpga: zynqmp: Use the scatterlist interface
• fpga: zynqmp: Initialized variables before using it
• fpga: zynqmp: Fix incorrect variables type

Commits:

• 4823227 fpga: zynqmp: Use the scatterlist interface
• aac8be7 fpga: zynqmp: Initialized variables before using it
• 2899bc8 fpga: zynqmp: Fix incorrect variables type

2020.1

• None

2019.2

Summary:

• fpga: zynqmp-fpga: Adds status interface

Commits:

• 8e85861 fpga: zynqmp-fpga: Adds status interface

2019.1

Summary:

• fpga: Fix bitstream typo error
• Merge tag 'v4.19' into master
• fpga: ZynqMP: Adds support for Authentication of bitstreams usning User-key
• drivers: xilinx: Reorganize firmware driver for zynqmp
• drivers: Defer probe if firmware is not ready
• fpga: zynqmp: Revert Authentication of bitstreams using User-key changes
• fpga: zynqmp: Use SPDX license header

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• Added support for vivado generated bit and bin file loading
• Added support for PL configuration readback 
• Added support for clock framework 

Commits:

• daca3d fpga: zynqmp: Adds support to load vivado generated .bit and .bin files
• bd1f10  fpga: zynqmp-fpga: Add support for pl configuration readback
• 097ea7 fpga: zynqmp-fpga: Add support for clock framework 

2018.2
Summary:

• Added Support for Partial Reconfiguration

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