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Occasionally, bare-metal applications relying on the XilFPGA library may produce an error getting the DONE status.  See Answer Record 70504 for more details - https://www.xilinx.com/support/answers/70504.html 

Note1: If the user tries to load the Few considerations that user should be aware of in programming the PL/FPGA are as follows.

• If the user tries to load the un-aligned bit/bin file the PL configuration takes a longer time when compared with aligned(word-aligned) bit/bin files.

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• Using overlay’s we can add a new node or add/update the existing node properties. But it will not allow replacing the existing nodes which is already part of the live tree. 
• If the PL design is having axi-intc IP, the relevant DT node should be the top-node in the overlay.dtsi or pl.dtsi file before its actually being referenced in any other nodes.

Example DT node.

/dts-v1/;
/plugin/;
/ {
	fragment@0 {
		target = <&fpga_full>;
		overlay0: __overlay__ {
			#address-cells = <2>;
			#size-cells = <2>;
			firmware-name = "system.bit.bin";
			resets = <&zynqmp_reset 116>;
		};
	};
	fragment@1 {
		target = <&amba>;
		overlay1: __overlay__ {
			afi0: afi0 {
				compatible = "xlnx,afi-fpga";
				config-afi = < 0 0>, <1 0>, <2 0>, <3 0>, <4 0>, <5 0>, <6 0>, <7 0>, <8 0>, <9 0>, <10 0>, <11 0>, <12 0>, <13 0>, <14 0xa00>, <15 0x000>;
			};
		};
	};
	fragment@2 {
		target = <&amba>;
		overlay2: __overlay__ {
			#address-cells = <2>;
			#size-cells = <2>;
			axi_intc_1: interrupt-controller@a00d0000 { /* Top node */
				#interrupt-cells = <2>;
				clock-names = "s_axi_aclk";
				clocks = <&clk_wiz_0 0>;
				compatible = "xlnx,axi-intc-4.1", "xlnx,xps-intc-1.00.a";
				interrupt-controller ;
				interrupt-names = "irq";
				interrupt-parent = <&axi_intc_0>;
				interrupts = <1 2>;
				reg = <0x0 0xa00d0000 0x0 0x10000>;
				xlnx,kind-of-intr = <0x360>;
				xlnx,num-intr-inputs = <0xe>;
			};
			axi_iic_0: i2c@a0000000 {
				#address-cells = <1>;
				#size-cells = <0>;
				clock-names = "s_axi_aclk";
				clocks = <&clk_wiz_0 0>;
				compatible = "xlnx,axi-iic-2.1", "xlnx,xps-iic-2.00.a";
				interrupt-names = "iic2intc_irpt";
				interrupt-parent = <&gic>;
				interrupts = <0 91 4>;
				reg = <0x0 0xa0000000 0x0 0x1000>;
			};
			axi_iic_1: i2c@a0008000 {
				#address-cells = <1>;
				#size-cells = <0>;
				clock-names = "s_axi_aclk";
				clocks = <&clk_wiz_0 0>;
				compatible = "xlnx,axi-iic-2.1", "xlnx,xps-iic-2.00.a";
				interrupt-names = "iic2intc_irpt";
				interrupt-parent = <&axi_intc_1>;
				interrupts = <1 2>;
				reg = <0x0 0xa0008000 0x0 0x1000>;
			};
		};
	};
};

Summary Table for Partial Reconfiguration / Dynamic Function Exchange Feature Support

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$ petalinux-build

Once build is complete, binaries are available at images/linux directory            

      5. Boot the hardware with newly built images

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$ bitbake petalinux-image-minimal

Once build is complete, binaries are available at ${DEPLOY_DIR_IMAGE} (${TMPDIR}/deploy/images/${MACHINE}/) directory            

      3. Boot the hardware with newly built images

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root@xilinx-zcu102-2018_3:~# fpgautil -r readbackdata -t 1
root@xilinx-zcu102-2018_3:~# hexdump readbackdata.bin > data.txt

Verification of Read-back Data

• To verify the readback data stream, compare it to the RBD golden readback file and masking readback bits with the MSD file. This approach is simple because there is a 1:1 correspondence between the start of the readback data stream and the start of the RBD and MSD files, making the task of aligning readback, mask, and expected data easier.

• The RBD and MSD files contain an ASCII representation of the readback and mask data along with a file header that lists the file name, etc. This header information should be ignored or deleted. The ASCII 1s and 0s in the RBD and MSD files correspond to the binary readback data from the device.

• For generating RBD and MSD refer UG908 (Vivado Design Suite User Guide)

  By compiling the below utility(verify_readback.c file) user can verify the read back contents.
  Source code: verify_readback

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Steps for programming the Full Bitstream 

Set flags for Full Bitstream

• echo 0 > /sys/class/fpga_manager/fpga0/flags

...

...

Steps for Readback of Configuration Registers

Set flags for readback type

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Steps for Readback of Configuration DataFrames 

Set flags for readback type

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Refer this link: libdfx - Linux User Space Solution for FPGA Programming

Mainline Status

The current driver availble in the xilinx linux git is in sync with the open source 4.19 kernel driver except for the following

• Encrypted and Authenticated Full/Partial Bitstream loading
• Readback of Configuration Registers
• Readback of Bitstream(Configuration Data)

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• FPGA Manager framework upgraded to 5.10v

2020.2

Summary:

• fpga: zynqmp: Use the scatterlist interface
• fpga: zynqmp: Initialized variables before using it
• fpga: zynqmp: Fix incorrect variables type

Commits:

• 4823227 fpga: zynqmp: Use the scatterlist interface
• aac8be7 fpga: zynqmp: Initialized variables before using it
• 2899bc8 fpga: zynqmp: Fix incorrect variables type

2020.1

• None

2019.2

Summary:

• fpga: zynqmp-fpga: Adds status interface

Commits:

• 8e85861 fpga: zynqmp-fpga: Adds status interface

2019.1

Summary:

• fpga: Fix bitstream typo error
• Merge tag 'v4.19' into master
• fpga: ZynqMP: Adds support for Authentication of bitstreams usning User-key
• drivers: xilinx: Reorganize firmware driver for zynqmp
• drivers: Defer probe if firmware is not ready
• fpga: zynqmp: Revert Authentication of bitstreams using User-key changes
• fpga: zynqmp: Use SPDX license header

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• Added support for vivado generated bit and bin file loading
• Added support for PL configuration readback 
• Added support for clock framework 

Commits:

• daca3d fpga: zynqmp: Adds support to load vivado generated .bit and .bin files
• bd1f10  fpga: zynqmp-fpga: Add support for pl configuration readback
• 097ea7 fpga: zynqmp-fpga: Add support for clock framework 

2018.2
Summary:

• Added Support for Partial Reconfiguration

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