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This page gives an overview of the zynqmp_nvmem driver which is available as part of the ZynqMP Linux distribution. Paths, files, links and documentation on this page are given relative to the Linux kernel source tree.


HW IP Features

  • SoC revision information
  • Efuse memory access.

Features supported in driver

  • SoC revision information
  • Programming and reading efuse memory

Missing Features, Known Issues and Limitations

  • None.

Kernel Configuration

Device Drivers ---> NVMEM Support ---> <*> Xilinx ZYNQMP SoC ID suppor
Image Modified


Code Block
nvmem_firmware {
compatible = "xlnx,zynqmp-nvmem-fw";
#address-cells = <1>;
#size-cells = <1>;

soc_revision: soc_revision@0 {
          reg = <0x0 0x4>;
/* efuse access */
efuse_dna: efuse_dna@c {
         reg = <0xc 0xc>;
efuse_usr0: efuse_usr0@20 {
         reg = <0x20 0x4>;
efuse_usr1: efuse_usr1@24 {
         reg = <0x24 0x4>;
efuse_usr2: efuse_usr2@28 {
        reg = <0x28 0x4>;
efuse_usr3: efuse_usr3@2c {
       reg = <0x2c 0x4>;
efuse_usr4: efuse_usr4@30 {
       reg = <0x30 0x4>;
efuse_usr5: efuse_usr5@34 {
       reg = <0x34 0x4>;
efuse_usr6: efuse_usr6@38 {
      reg = <0x38 0x4>;
efuse_usr7: efuse_usr7@3c {
        reg = <0x3c 0x4>;
efuse_miscusr: efuse_miscusr@40 {
       reg = <0x40 0x4>;
efuse_chash: efuse_chash@50 {
       reg = <0x50 0x4>;
efuse_pufmisc: efuse_pufmisc@54 {
       reg = <0x54 0x4>;
efuse_sec: efuse_sec@58 {
       reg = <0x58 0x4>;
efuse_spkid: efuse_spkid@5c {
       reg = <0x5c 0x4>;
efuse_ppk0hash: efuse_ppk0hash@a0 {
       reg = <0xa0 0x30>;
efuse_ppk1hash: efuse_ppk1hash@d0 {
      reg = <0xd0 0x30>;



To access efuse memory, PMUFW should be built by enabling ENABLE_EFUSE_ACCESS in xpfw_config.h and the respective eFuse classification macro to access read/write. By default this is disabled. But revision at offset 0x0 is enabled by default. Once booted into Linux, to read/write particular field please do read/write from/to "/sys/bus/nvmem/devices/zynqmp-nvmem0/nvmem" to the particular offset with the corresponding size.

Following are the respective eFuse classification macro to access read/write

  • To access User0 to User7 (Offset 0x20 to 0x3C) efuse register, PMUFW should be built by defining  XSK_ACCESS_USER_EFUSE as well in "lib/sw_services/xilskey/include/xilskey_eps_zynqmp.h".
  • To access SPK ID, AES KEY, PPK0 hash and PPK1 hash efuse register, PMUFW should be built by defining  XSK_ACCESS_KEY_MANAGE_EFUSE as well in "lib/sw_services/xilskey/include/xilskey_eps_zynqmp.h".

The following table gives the overview of possible addresses for read/write and with the sizes.


RegisterSize in bytes(hex)Offset (hex)bs(dec)count(dec)skip(dec)
SPK ID45C4123
Secure Control4584122
PPK1 hash30D041252
PPK0 hash30A041240
Misc user4404116

Known Limitation : dd command can be used to read one word of data only (This means bs =4 and count =1). Therefore dd command cannot be used for reading PPK0/1. Linux application provided in wiki page can be used to read PPK0/1 values . 

Using linux application

As an alternative to dd command, a linux application can be used to read/write into eFuse from linux.