This page gives an overview of the Zynq Ultrascale+ This page gives an overview of the Zynq Ultrascale+ MPSoC Clock framework available at drivers/clk/zynqmp/. For CCF to work, PMUFW should be downloaded.
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Symbol: COMMON_CLK_ZYNQMP [=y] │ │ Type : boolean │
│ Prompt: Support for Xilinx ZynqMP Ultrascale+ clock controllers │
│ Location: │
│ -> Device Drivers │
│ (1) -> Common Clock Framework │
│ Defined at drivers/clk/zynqmp/Kconfig:1 │
│ Depends on: COMMON_CLK [=y] &&&& OF [=y] &&&& (ARCH_ZYNQMP [=y] || COMPILE_TEST [=n]) |
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- i2c
- qspi
- sd card
- nand
- uart
- gem
- gpio
- dma
- sata
- apm
Data rate change is tested with gem.
Sample expected log is below
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root@Xilinx-ZCU102-2016_2:~# ethtool -s eth0 speed 1000 duplex full root@Xilinx-ZCU102-2016_2:~# [ 1168.866072] macb ff0e0000.ethernet eth0: link down Received IPI Mask:0x00000001 PMUFW: PmMmioRead: (NODE_APU) addr=0xFF5E005C, value=0x6050C00 Received IPI Mask:0x00000001 PMUFW: PmMmioWrite: (NODE_APU) addr=0xFF5E005C, mask=0xFFFFFFFF, value=0x6010C00 Received IPI Mask:0x00000001 PMUFW: PmMmioRead: (NODE_APU) addr=0xFF5E005C, value=0x6010C00 [ 1170.890303] macb ff0e0000.ethernet eth0: link up (1000/Full) |
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root@Xilinx-ZCU102-2016_2:~# ethtool -s eth0 speed 10 duplex full
root@Xilinx-ZCU102-2016_2:~# [ 1192.898072] macb ff0e0000.ethernet
eth0: link down
Received IPI Mask:0x00000001
PMUFW: PmMmioRead: (NODE_APU) addr=0xFF5E005C, value=0x6010C00
Received IPI Mask:0x00000001
PMUFW: PmMmioWrite: (NODE_APU) addr=0xFF5E005C, mask=0xFFFFFFFF, value=0x6320C00
Received IPI Mask:0x00000001
PMUFW: PmMmioRead: (NODE_APU) addr=0xFF5E005C, value=0x6320C00
[ 1195.922279] macb ff0e0000.ethernet eth0: link up (10/Full)
root@Xilinx-ZCU102-2016_2:~# |
Debug
View the Clock configuration summary.
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cat /sys/kernel/debug/clk/clk_summary
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Change log
2016.3
Summary:
- Adds basic clock support for zynqmp.
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- the GEM mux shift values are corrected.
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- The watchdog source is corrected.
- Since for dp to work it changes the parent rate. We do not support dp sharing the parent (VPLL).A warn is added to check for the same.
- Sets the set rate parent for video clocks.
- Fractional mode support is enabled.
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- In some cases the second divisor was was getting saturated resulting in some ethernet failures.this is fixed.
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- Fix the usb mux offset
- Some waning fixes
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- Remove unused variables
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- Move MMIO error to debug from warn
- Use SPDX license
- Replace clock driver with new driver which fetches clock information from firmware
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- clk: zynqmp: Move a warn to debug
- clk: zynqmp: Use SPDX and update author
- clk: zynqmp: Use firmware APIs in clock driver
- clk: zynqmp: Fix reserved parent comparision
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- None
2018.3
- None
2019.1
Summary:
- clk: zynqmp: Extend driver for versal
- clk: zynqmp: fix doc of __zynqmp_clock_get_parents
- clk: zynqmp: Add support for custom type flags
- drivers: Defer probe if firmware is not ready
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- clk: zynqmp: Extend driver for versal
- clk: zynqmp: fix doc of __zynqmp_clock_get_parents
- clk: zynqmp: Add support for custom type flags
- drivers: clk: Update clock driver to handle clock attribute
.922279] macb ff0e0000.ethernet eth0: link up (10/Full)
root@Xilinx-ZCU102-2016_2:~# |
Debug
View the Clock configuration summary.
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cat /sys/kernel/debug/clk/clk_summary
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Porting to CCF
Porting to CCF
Mainline status
Mainlined
Change log
2024.1
None
2023.2
None
2023.1
Summary:
- clk: zynqmp: pll: Remove the limit
- clk: zynqmp: pll: rectify rate rounding in zynqmp_pll_round_rate
Commits:
2020.2
Summary:
- clk: zynqmp: Handle divider specific read only flag
- clk: zynqmp: Use firmware specific common clock flags
- clk: zynqmp: Use firmware specific mux clock flags
- clk: zynqmp: Add missing checking of eemi_ops
- clk: zynqmp: Add a check for NULL pointer
- clk: zynqmp: Make zynqmp_clk_get_max_divisor static
- clk: zynqmp: make bestdiv unsigned
Commits:
- clk: zynqmp: Handle divider specific read only flag
- clk: zynqmp: Use firmware specific common clock flags
- clk: zynqmp: Use firmware specific mux clock flags
- clk: zynqmp: Add missing checking of eemi_ops
- clk: zynqmp: Add a check for NULL pointer
- clk: zynqmp: Make zynqmp_clk_get_max_divisor static
- clk: zynqmp: make bestdiv unsigned
2022.2
None
2022.1
Summary:
- clk: zynqmp: Use firmware specific common clock flags
- clk: zynqmp: Use firmware specific divider clock flags
- clk: zynqmp: Use firmware specific mux clock flags
- clk: zynqmp: Handle divider specific read only flag
- clk: zynqmp: Fix kernel doc
- clk: zynqmp: Fix a memory leak
Commits:
- clk: zynqmp: Use firmware specific common clock flags
- clk: zynqmp: Use firmware specific divider clock flags
- clk: zynqmp: Use firmware specific mux clock flags
- clk: zynqmp: Handle divider specific read only flag
- clk: zynqmp: Fix a memory leak
2021.2
Summary:
- clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enable
- clk: zynqmp: divider: Align max_div description with mainline
- clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callback
- clk: zynqmp: pll: Remove some dead code
- clk: zynqmp: Enable the driver if ZYNQMP_FIRMWARE is selected
- clk: zynqmp: Sync with mainline
Commits:
- clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enable
- clk: zynqmp: divider: Align max_div description with mainline
- clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callback
- clk: zynqmp: pll: Remove some dead code
- clk: zynqmp: Enable the driver if ZYNQMP_FIRMWARE is selected
- clk: zynqmp: Sync with mainline
2021.1
- None
2020.1
Summary:
- clk: zynqmp: Fix CLK_FRAC bit index
- clk: zynqmp: Fix missing max_div description in kernel-doc format
- clk: zynqmp: Fix divider2 calculation
- clk: zynqmp: fix memory leak in zynqmp_register_clocks
- drivers: clk: Fix invalid clock name queries
Commits:
- clk: zynqmp: Fix CLK_FRAC bit index
- clk: zynqmp: Fix missing max_div description in kernel-doc format
- clk: zynqmp: Fix divider2 calculation
- clk: zynqmp: fix memory leak in zynqmp_register_clocks
- drivers: clk: Fix invalid clock name queries
2019.2
Summary:
- clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag
- clk: zynqmp: Recalculate bestdiv for DIV2 clock
- clk: zynqmp: Warn user if clock user are more than allowed
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- clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag
- clk: zynqmp: Recalculate bestdiv for DIV2 clock
- clk: zynqmp: Warn user if clock user are more than allowed
20202019.1
Summary:
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Summary:
- clk: zynqmp: Fix divider2 calculationExtend driver for versal
- clk: zynqmp: fix memory leak in doc of __zynqmp_register_clocksdrivers: clk: Fix invalid clock name queriesclock_get_parents
- clk: zynqmp: Add support for custom type flags
- drivers: Defer probe if firmware is not ready
Commits:
- clk: zynqmp: Fix CLK_FRAC bit indexExtend driver for versal
- clk: zynqmp: Fix missing max_div description in kernel-doc formatfix doc of __zynqmp_clock_get_parents
- clk: zynqmp: Fix divider2 calculation
- clk: zynqmp: fix memory leak in zynqmp_register_clocks
- drivers: clk: Fix invalid clock name queries
2020.2
...
2018.3
- None
2018.2
- None
2018.1
Summary:
- Move MMIO error to debug from warn
- Use SPDX license
- Replace clock driver with new driver which fetches clock information from firmware
Commits:
- clk: zynqmp: Handle divider specific read only flagMove a warn to debug
- clk: zynqmp: Use firmware specific common clock flagsSPDX and update author
- clk: zynqmp: Use firmware specific mux APIs in clock flagsdriver
- clk: zynqmp: Add missing checking of eemi_ops
- clk: zynqmp: Add a check for NULL pointer
- clk: zynqmp: Make zynqmp_clk_get_max_divisor staticFix reserved parent comparision
- : make bestdiv unsigned
2017.4
Summary:
- Remove unused variables
Commits:
clk: zynqmp:
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2021.1
- None
2021.2
Summary:
- clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enable
- clk: zynqmp: divider: Align max_div description with mainline
- clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callback
- clk: zynqmp: pll: Remove some dead code
- clk: zynqmp: Enable the driver if ZYNQMP_FIRMWARE is selected
- clk: zynqmp: Sync with mainline
Commits:
- clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enable
- clk: zynqmp: divider: Align max_div description with mainline
- clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callback
- clk: zynqmp: pll: Remove some dead code
- clk: zynqmp: Enable the driver if ZYNQMP_FIRMWARE is selected
- clk: zynqmp: Sync with mainline
2022.1
Summary:
- clk: zynqmp: Use firmware specific common clock flags
- clk: zynqmp: Use firmware specific divider clock flags
- clk: zynqmp: Use firmware specific mux clock flags
- clk: zynqmp: Handle divider specific read only flag
- clk: zynqmp: Fix kernel doc
- clk: zynqmp: Fix a memory leak
Commits:
- clk: zynqmp: Use firmware specific common clock flags
- clk: zynqmp: Use firmware specific divider clock flags
- clk: zynqmp: Use firmware specific mux clock flags
- clk: zynqmp: Handle divider specific read only flag
- clk: zynqmp: Fix a memory leak
2022.2
None
2023.1
Summary:
- clk: zynqmp: pll: Remove the limit
- clk: zynqmp: pll: rectify rate rounding in zynqmp_pll_round_rate
Commits:
2023.2
None
2017.3
Summary:
- Fix the usb mux offset
- Some waning fixes
Commits:
clkc: zynqmp: fix the usb mux
zynqmp: Use new firmware.h instead of pm.h
clk: zynqmp: divider: Fix the warnings
clk: zynqmp: Remove variables set but not used
2017.2
Summary:
- In some cases the second divisor was was getting saturated resulting in some ethernet failures.this is fixed.
Commits:
clk: zynqmp: Let the frac be decided on the frac capability
2017.1
Summary:
- The watchdog source is corrected.
- Since for dp to work it changes the parent rate. We do not support dp sharing the parent (VPLL).A warn is added to check for the same.
- Sets the set rate parent for video clocks.
- Fractional mode support is enabled.
Commits:
clk: zynqmp: Fix the watchdog clock source
clk: zynqmp: Warn on vpll multiuser conditionally
pll: zynqmp: Add support for pll set rate
clk: zynqmp: Set the needed flags
clk: zynqmp: clkc: Enable CLK_SET_RATE_PARENT for more clocks
clk: Reset the child count
clk: zynqmp: pll: Enable the fractional mode when needed
clk: zynqmp: Prevent un-necessary rounding off
clk: zynqmp: Enhance the prints
2016.4
Summary:
- the GEM mux shift values are corrected.
Commits:
clk: zynqmp: Fix GEM mux shift values
2016.3
Summary:
- Adds basic clock support for zynqmp.
Commits:
clk: zynqmp: Add initial ccf clkc support
clk: zynqmp: add mux changes for zynqmp
f5e303d clk: zynqmp: Add zynqmp divider support
8592671 clk: zynqmp: Add zynqmp ultrascale gate support
ea2cd726 clk: zynqmp: Add the pll driver
4d85a2c clk: zynqmp: Fix GEM mux shift values
Related Links
- Linux Drivers
- DTG Common clock framework
- 2017.4 or earlier release clock DTSI
View file name zynqmp-clk.dtsi - 2018.1 DTSI
View file name zynqmp-clk-ccf.dtsi
o Missing features, Known Issues, limitationso