This page gives an overview of the Zynq Ultrascale+ MPSoC Clock framework available at drivers/clk/zynqmp/. For CCF to work, PMUFW should be downloaded.
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- i2c
- qspi
- sd card
- nand
- uart
- gem
- gpio
- dma
- sata
- apm
Data rate change is tested with gem.
Sample expected log is below
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|---|---|---|
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root@Xilinx-ZCU102-2016_2:~# ethtool -s eth0 speed 1000 duplex full root@Xilinx-ZCU102-2016_2:~# [ 1168.866072] macb ff0e0000.ethernet eth0: link down Received IPI Mask:0x00000001 PMUFW: PmMmioRead: (NODE_APU) addr=0xFF5E005C, value=0x6050C00 Received IPI Mask:0x00000001 PMUFW: PmMmioWrite: (NODE_APU) addr=0xFF5E005C, mask=0xFFFFFFFF, value=0x6010C00 Received IPI Mask:0x00000001 PMUFW: PmMmioRead: (NODE_APU) addr=0xFF5E005C, value=0x6010C00 [ 1170.890303] macb ff0e0000.ethernet eth0: link up (1000/Full) |
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- clk: zynqmp: Move a warn to debug
- clk: zynqmp: Use SPDX and update author
- clk: zynqmp: Use firmware APIs in clock driver
- clk: zynqmp: Fix reserved parent comparision
2018.2
- None
2018.3
- None
2019.1
Summary:
- clk: zynqmp: Extend driver for versal
- clk: zynqmp: fix doc of __zynqmp_clock_get_parents
- clk: zynqmp: Add support for custom type flags
- drivers: Defer probe if firmware is not ready
Commits:
- clk: zynqmp: Extend driver for versal
- clk: zynqmp: fix doc of __zynqmp_clock_get_parents
- clk: zynqmp: Add support for custom type flags
- drivers: clk: Update clock driver to handle clock attribute
2019.2
Summary:
- clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag
- clk: zynqmp: Recalculate bestdiv for DIV2 clock
- clk: zynqmp: Warn user if clock user are more than allowed
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- clk: zynqmp: Fix CLK_FRAC bit index
- clk: zynqmp: Fix missing max_div description in kernel-doc format
- clk: zynqmp: Fix divider2 calculation
- clk: zynqmp: fix memory leak in zynqmp_register_clocks
- drivers: clk: Fix invalid clock name queries
2020.2
Summary:
- clk: zynqmp: Handle divider specific read only flag
- clk: zynqmp: Use firmware specific common clock flags
- clk: zynqmp: Use firmware specific mux clock flags
- clk: zynqmp: Add missing checking of eemi_ops
- clk: zynqmp: Add a check for NULL pointer
- clk: zynqmp: Make zynqmp_clk_get_max_divisor static
- clk: zynqmp: make bestdiv unsigned
Commits:
- clk: zynqmp: Handle divider specific read only flag
- clk: zynqmp: Use firmware specific common clock flags
- clk: zynqmp: Use firmware specific mux clock flags
- clk: zynqmp: Add missing checking of eemi_ops
- clk: zynqmp: Add a check for NULL pointer
- clk: zynqmp: Make zynqmp_clk_get_max_divisor static
- clk: zynqmp: make bestdiv unsigned
2021.1
- None
Related Links
- Linux Drivers
- DTG Common clock framework
- 2017.4 or earlier release clock DTSI
View file name zynqmp-clk.dtsi - 2018.1 DTSI
View file name zynqmp-clk-ccf.dtsi
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