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ZynqMP firmware

Zynq Ultrascale+ MPSoC/Versal  firmware driver

Firmware interface driver for Zynq Ultrascale+ MPSoC/Versal


Introduction


ZynqMP has an interface to communicate with secure firmware. Firmware driver provides an interface to firmware APIs. Interface APIs can be used by any driver to communicate to PMUFW(Platform Management Unit)(ZynqMP) or PLM(Platform Loader and Manager)(Versal). These requests include clock management, pin control, device control, power management service, FPGA service and other platform management services.

HW IP features

NA

Features supported in driver

  • Communication layer to request Platform Management Unit and Trustzone
  • Control/configure devices through IOCTL
  • Query platform specific information from firmware
  • Clock control
  • Pin control and configurations
  • other platform management services like FPGA management, reset, etc
  • Debug interface to debug firmware APIs
  • Sysfs interface for accessing GGS and PGGS registers, setting shutdown scope, setting health boot status, accessing PMU and CSU registers

Missing Features, Known Issues and Limitations

None

Kernel Configuration

Firmware driver is by default enabled for ZynqMP platform. The following config options should be enabled in order to build the ZynqMP firmware driver:
Code Block
themeMidnight
CONFIG_ZYNQMP_FIRMWARE:
 
Firmware interface driver is used by different to
communicate with the firmware for various platform
management services.
Say yes to enable ZynqMP firmware interface driver.
In doubt, say N
 
Symbol: ZYNQMP_FIRMWARE [=y]
Type  : boolean
Prompt: Enable Xilinx Zynq MPSoC firmware interface
  Location:
    -> Firmware Drivers
      -> Zynq MPSoC Firmware Drivers
  Defined at drivers/firmware/xilinx/zynqmp/Kconfig:7
  Depends on: ARCH_ZYNQMP [=y]
  Selected by: ARCH_ZYNQMP [=y]


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