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This page gives an overview of axi ethernet driver which is available as part of the Xilinx Vivado and SDK distribution
This page gives an overview of the bare-metal driver support for the Xilinx® AXI 1G/2.5G Ethernet Subsystem soft IP.   


Table of Contents

Table of Contents

Introduction

excludeTable of Contents

Introduction


The AXI 1G/2.5G Ethernet Subsystem core is a soft Xilinx IP core for use with the Xilinx Vivado® Design Suite. The Xilinx® AXI Ethernet Subsystem implements a tri-mode (10/100/1000 Mb/s) Ethernet MAC or a 10/100 Mb/s Ethernet MAC. This core supports the use of MII, GMII, SGMII, RGMII, and 1000BASE-X interfaces to connect a media access control (MAC) to a Physical-side interface (PHY) chip. It also provides an on-chip PHY for 1G/2.5G SGMII and 1000/2500 BASE-X modes. The MDIO interface is used to access PHY Management registers. This subsystem optionally enables TCP/UDP full checksum Offload, VLAN stripping, tagging, translation and extended filtering for multicast frames features.

How to enable

Source Path for the driver

For more information, please refer to the AXI Ethernet product page which includes links to the official documentation and resource utilization. 

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository. 

<If there are multiple drivers supporting this IP, we should make that statement here and add to the table>


Driver NamePath in VitisPath in Github
axiethernet<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/axiethernet_<version>https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/axiethernet


Info

Note: To view the sources for a particular release, use the rel-version tag in github.  For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/axiethernet

Driver


The driver source code is organized into different folders.

Below diagram

  The table below shows the axiethernet driver source organization. 

axiethernet


Directory
|
Description
-
doc
-

Provides the API and data structure details

| 
data
- data -
Driver .tcl and
MDD
.mdd file
.
|
- examples - Reference application to
examplesExample applications that show how to use the driver
APIs and calling sequence
|
- src-
features
srcDriver source files

Features Supported

Controller Features

  • Support for MII, GMII, RGMII, SGMII, and 1000BASE-X PHY interfaces
  • Support for 1000BASE-X and SGMII over Select Input/Output (I/O) Low Voltage Differential Signaling (LVDS)
  • Support for pause frames for flow control
  • Media Independent Interface Management (also called as MII), is used for accessing the PHY registers
  • Ethernet Audio Video Bridging (AVB) support
  • AXI4-Stream transmit/receive interface
  • Support for 2.5G Ethernet. This feature is enabled for the following devices: Kintex®-7, Virtex®-7 with GTH and GTX transceivers Artix®-7 devices with GTP and speed grade -2 and -3 UltraScale™, UltraScale+™ devices with GTH and GTY transceivers
  • IEEE Standard 1588 Support
  • AXI4-Lite register interface

Standalone Driver Supported Features

The AXI Ethernet Standalone driver supports the below things.


Driver Implementation

For a full list of features supported by this IP, please refer to the AXI Ethernet product page.  


Features

The AXI Ethernet Standalone driver supports the following features: 
  • Supports all 1G phy-interface types MII, GMII, RGMII, SGMII and 1000base-x
  • Supports VLAN Frames
  • Supports Pause frames and flow control features
  • Support for AXI DMA Ethernet-based designs
  • Support for Axi Ethernet FIFO based designs
  • Support for Axi MCDMA Ethernet-based designs
  • Supports different Speeds 10/100/1000 Mbps
  • Supports Partial/Full Checksum offloading
  • Supports 2.5G buffered mode feature.
Features not supportedRefer to

Known Issues and Limitations

The following is a list of known limitations of the driver and features of the IP that are not currently implemented: 

  • IEEE 1588 feature is not supported
  • No Support when 2.5G Ethernet is configured for Non-Buffered/Processor mode
  • No Support when 1G Ethernet is configured in Non-Buffered/Processor Mode

Interop

- PHY device Marvell 88E1116 has been tested on KC705 evaluation board
- PHY device TI DP83867 SGMII have been tested on VCU118 board.

Test cases

Axi Ethernet DMA Example
Axi Ethernet basic AXI DMA loopback example can be tested by selecting xaxiethernet_example_intr_sgdma.c, xaxiethernet_example_util.c and xaxiethernet_example.h from the driver.

Example Design Architecture 

The examples assumes that AXI Ethernet AXI4-Stream bus is connected to AXIDMA/MCMDA/FIFO IP. 

Image Added



Example Applications

Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications.  These example applications can be imported into the Vitis IDE from the Board Support Package  settings tab. 

Links to Examples

Examples Path: https://github.com/Xilinx/embeddedsw/

blob

tree/master/XilinxProcessorIPLib/drivers/axiethernet/examples

/readme.txt for more information.
Axi Ethernet FIFO Example
Axi Ethernet basic AXI FIFO loopback example can be tested by selecting


Test NameExample SourceDescription
Frame transfer with FIFO interruptxaxiethernet_example_intr_fifo.cThis example utilize the Axi Ethernet interrupt driven FIFO packet transfer mode to send and receive frames.
Frame transfer with FIFO pollingxaxiethernet_example_polled.cThis example utilize the Axi Ethernet polling driven FIFO packet transfer mode to send and receive frames.
Frame transfer with MCMDA interruptxaxiethernet_example_intr_
fifo.c,
mcdma.cThis example utilize the Axi Ethernet interrupt driven MCDMA packet transfer mode to send and receive frames.
Frame transfer with MCMDA pollingxaxiethernet_example_mcdma_
util
poll.cThis example utilize the Axi Ethernet polling driven MCDMA packet transfer mode to send and receive frames.
Frame transfer with AXIDMA SG interruptxaxiethernet_example
.h from the driver.
Refer to https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/axiethernet/examples/readme.txt for more information.
Known Issues/Limitations
  • At the h/w level if the MAC reference clock is driving from onboard clock oscillator e.g si570 or si5324. Make sure clock is programmed to the proper clock value before performing any operations on the MAC.

Changelog

2020.2

  • Support parallel make execution. 
  • Add versal support.
  • Fix bsp generation error in a custom design.

257c0d9e3742 BSP: Consolidate and add the drivers xdebug.h data to common xdebug.h
4dc85994d6fb Makefile: Remove realpath command
ad4739446424 axiethernet: Modify makefile to support parallel make execution
14a8bb9f1bc8 axiethernet: Add support for versal silicon
300a9c894a55 axiethernet: Fix bsp generation error in a custom design

2020.1

  • Clean up old versions for axiethernet driver
  • In debug mode fix return value of XAxiEthernet_ReadReg
  • In driver tcl use "::hsi::utils::get_connected_intf" API
  • Trivial code cleanup i.e Removed the assert condition for speed

500b39a axiethernet: Clean up old versions for axiethernet driver
5191a3a axiethernet: In debug mode fix return value of XAxiEthernet_ReadReg
14eefd8 axiethernet: In driver tcl use "::hsi::utils::get_connected_intf" API
acf82d5 axiethernet: Removed the assert condition for speed.

2019.2

  • None

2019.1

  • In driver tcl use an identifiable suffix for global variables

Commit ID's

db36090 axiethernet: Use an identifiable suffix for global variables

2018.3

  • In SG interrupt example set BD length to jumbo frame size.
  • Fix interrupt ID generation for ZynqMP designs.
  • In driver tcl improve error message for non-supported HW designs.
  • Fix cppcheck and gcc warnings.

c676978 Fix error 'committing RxBD to HW' in SG dma interrupt example
3e6fd05 Fix interrupt ID generation for ZynqMP designs
fc025e0 Improve error message for non-supported HW designs
6b2c516 examples: Fix gcc [-Wint-conversion] warning
9711443 Include missing initializers for 'XAxiEthernet_Config' fields
2d15ad1 Fix cppcheck warnings

2018.2
  • None
2018.1
  • Fix compilation issues in multicast/extvlan example.
  • Set num of multicast table entries parameter based on hw design.
  • Use table entries count from config structure.
  • Used UINTPTR type for DMA BaseAddress.
  • Implementing poll timeout API in the axiethernet driver.
4ea9f9d axiethernet: Fix compilation issues in multicast/extvlan example
5fa4d74 Set num of multicast table entries parameter based on hw design
abe45ad axiethernet: Use table entries count from config structure
ee523e1 axiethernet: Used UINTPTR type for DMA BaseAddress
1866fc8 Axiethernet: Implementing poll timeout API in the axiethernet driver
2017.4:
  • None.
2017.3
  • Added support for Ethernet MCDMA Configuration in the driver
  • Added axi ethernet mcdma examples.
  • Fixed issues with Chipscope designs
  • Fix pmufw compilation errors for Ethernet mcdma based designs.
Commit ID's
60104ac : axiethernet: Add support for mcdma
2ad67e6 : axiethernet: Add axiethernet mcdma examples
14c3ca9 : axiethernet: Fix issues with the chipscope designs
2e47d70 : axiethernet: Fix pmufw compilation errors
2017.2
  • Increase timeout values in the driver as per new h/w updates for ultrascale+ devices
Commit ID
ef2ffba: Increase timeout values
2017.1
  • Added Support for TI PHY (DP83867)
Commit ID
a523a1d : Add Support for TI PHY in the peripheral test
_intr_sgdma.cThis example utilize the Axi Ethernet interrupt driven SGDMA mode to send and receive frames.
Ping request with MCDMA pollingxaxiethernet_mcdma_ping_req_example.cThis example utilize the Axi Ethernet polling driven MCDMA packet transfer mode to send ping request frames.
Extended multicast with AXI DMA SG interruptxaxiethernet_example_extmulticast.cThis example utilize the Axi Ethernet interrupt driven SGDMA packet transfer mode to send and receive frames.
It demonstrates the extended multicast capability
Extended VLAN with AXI DMA SG interruptxaxiethernet_example_extvlan.cThis example utilize the Axi Ethernet interrupt driven SGDMA packet transfer mode to send and receive frames.
It demonstrates the extended VLAN capability

Example Application Usage

Frame transfer with FIFO interrupt

This example utilize the Axi Ethernet interrupt driven FIFO packet transfer mode to send and receive frames.

Expected Output

Code Block
themeMidnight
--- Enter main() ---
This test may take several minutes to finish
Successfully ran Axiethernet intr fifo Example
--- Exiting main() ---

Frame transfer with FIFO polling

This example utilize the Axi Ethernet polling driven FIFO packet transfer mode to send and receive frames.

Expected Output

Code Block
themeMidnight
--- Enter main() ---
This test may take several minutes to finish
Successfully ran Axiethernet poll mode fifo Example
--- Exiting main() ---

Frame transfer with MCMDA interrupt

This example utilize the Axi Ethernet interrupt driven MCDMA packet transfer mode to send and receive frames.

Expected Output

Code Block
themeMidnight
--- Enter main() ---
This test may take several minutes to finish
Test passed
--- Exiting main() ---

Frame transfer with MCMDA polling

This example utilize the Axi Ethernet polling driven MCDMA packet transfer mode to send and receive frames.

Expected Output

Code Block
themeMidnight
--- Enter main() ---
This test may take several minutes to finish
Polled Mode Test passed
--- Exiting main() ---

Frame transfer with AXIDMA SG interrupt

This example utilize the Axi Ethernet interrupt driven SGDMA mode to send and receive frames.

Expected Output

Code Block
themeMidnight
--- Enter main() ---
This test may take several minutes to finish
Successfully ran Axiethernet intr sgdma Example
--- Exiting main() ---

Ping request with MCDMA polling

This example utilize the Axi Ethernet polling driven MCDMA packet transfer mode to send ping request frames.

Expected Output

Code Block
themeMidnight
DMA init success
Cfg init success
BD seutp done
Successfully ran Axi Ethernet ping request Example

Extended multicast with AXI DMA SG interrupt

This example utilize the Axi Ethernet interrupt driven SGDMA packet transfer mode to send and receive frames. It demonstrates the extended multicast capability

Expected Output

Code Block
themeMidnight
--- Enter main() ---
This test may take several minutes to finish
Successfully ran Axiethernet extmulticast Example
--- Exiting main() ---

Extended VLAN with AXI DMA SG interrupt

This example utilize the Axi Ethernet interrupt driven SGDMA packet transfer mode to send and receive frames. It demonstrates the extended VLAN capability

Expected Output

Code Block
themeMidnight
--- Enter main() ---
This test may take several minutes to finish
Successfully ran Axiethernet extvlan Example
--- Exiting main() ---


Change Log

2021.2

https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2021.2/doc/ChangeLog#L72

2021.1

https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2021.1/doc/ChangeLog#L403


Related Links